arm7
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：169KB
下载次数：83
上传日期：2009-12-02 10:57:51
上 传 者：
blue1101
说明： ARM7 VERILOG源码，非常精简，3级流水线
(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
文件列表:
fpga\arm6.v (57393, 2009-06-08)
fpga\arm_sp.v (3564, 2009-05-01)
fpga\arm_top.ucf (1280, 2009-05-06)
fpga\arm_top.v (8087, 2009-05-07)
fpga\dll.v (2857, 2009-05-04)
fpga\dll.xaw (3214, 2009-05-03)
fpga\dll_arwz.ucf (728, 2009-05-04)
fpga\ram.asy (596, 2009-05-03)
fpga\ram.ngc (5108, 2009-05-03)
fpga\ram.sym (947, 2009-05-03)
fpga\ram.v (4028, 2009-05-03)
fpga\ram.veo (3035, 2009-05-03)
fpga\ram.vhd (4555, 2009-05-03)
fpga\ram.vho (3512, 2009-05-03)
fpga\ram.xco (1778, 2009-05-03)
fpga\ram_flist.txt (133, 2009-05-03)
fpga\ram_xmdf.tcl (2936, 2009-05-03)
fpga\rom.asy (598, 2009-05-05)
fpga\rom.coe (9516, 2009-05-05)
fpga\rom.mif (29206, 2009-05-05)
fpga\rom.ngc (20629, 2009-05-05)
fpga\rom.sym (952, 2009-05-05)
fpga\rom.v (4025, 2009-05-05)
fpga\rom.veo (3037, 2009-05-05)
fpga\rom.vhd (4554, 2009-05-05)
fpga\rom.vho (3514, 2009-05-05)
fpga\rom.xco (1830, 2009-05-05)
fpga\rom_flist.txt (142, 2009-05-05)
fpga\rom_xmdf.tcl (3096, 2009-05-05)
fpga\rxtx.v (2852, 2009-05-06)
fpga\test.ise (384918, 2009-05-07)
fpga (0, 2009-06-15)
The following files were generated for 'ram' in directory
F:\proj\arm\fpga\test:
ram.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ram.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ram.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
ram.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
ram.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
ram.sym:
Please see the core data sheet.
ram.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ram.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ram_xmdf.tcl:
Please see the core data sheet.
ram_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
ram_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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