uart_receive
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：11KB
下载次数：98
上传日期：2009-12-05 20:29:35
上 传 者：
zyfei
说明： 串口接收数据44个8bit数据，并且将4个8bit数拼接成32bit数，存进ram中，
可以通过 in system memory editro 查看
(Serial port receive data 44 8bit data, and will be spliced into four 8bit number of 32bit number, deposit into the ram in, you can see in system memory editro)
文件列表:
uart_receive\baudrate9600.v (17151, 2009-12-01)
uart_receive\c2b32.v (7728, 2009-12-01)
uart_receive\dpram128_32.v (10681, 2009-12-01)
uart_receive\emif_receive.v (1283, 2009-12-01)
uart_receive\emif_receive_top.v (1610, 2009-12-01)
uart_receive\pin.tcl (2592, 2009-12-01)
uart_receive\ram128_32bit.v (7128, 2009-11-30)
uart_receive (0, 2009-12-05)
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