My_Clock
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：572KB
下载次数：20
上传日期：2009-12-05 23:16:04
上 传 者：
jemofh
说明： 发个我的第一个VHDL代码，秒表。可暂停继续.清0。
(My first one made a VHDL code, and a stopwatch. Continue to be suspended. Qing 0.)
文件列表:
My_Clock\BCD_7SEG.vhd (1195, 2009-12-05)
My_Clock\clk_1Hz.map.rpt (30893, 2009-11-17)
My_Clock\clk_1Hz.flow.rpt (5428, 2009-11-17)
My_Clock\BCD_7SEG.vhd.bak (964, 2009-11-17)
My_Clock\CTR_MOD_10.vhd.bak (574, 2009-11-14)
My_Clock\CTR_MOD_10.vhd (814, 2009-12-05)
My_Clock\CTR_MOD_6.vhd (807, 2009-12-05)
My_Clock\CTR_MOD_2.vhd (807, 2009-12-05)
My_Clock\MyClock.bdf (6366, 2009-11-14)
My_Clock\clk_1Hz.bsf (2130, 2009-11-17)
My_Clock\BCD_7SEG.bsf (1776, 2009-11-17)
My_Clock\CTR_MOD_10.bsf (1764, 2009-11-14)
My_Clock\CTR_MOD_6.bsf (1763, 2009-11-14)
My_Clock\CTR_MOD_2.bsf (1763, 2009-11-14)
My_Clock\CTR_MOD_6.vhd.bak (571, 2009-11-14)
My_Clock\CTR_MOD_2.vhd.bak (477, 2009-11-14)
My_Clock\shift.vhd (964, 2009-12-05)
My_Clock\shift.vhd.bak (717, 2009-11-14)
My_Clock\shift.bsf (1580, 2009-11-14)
My_Clock\shift_.vhd (1161, 2009-12-05)
My_Clock\shift_.vhd.bak (920, 2009-11-14)
My_Clock\shift_en.bsf (2821, 2009-11-14)
My_Clock\clk_1Hz.pin (27578, 2009-11-17)
My_Clock\clk_1Hz.fit.smsg (513, 2009-11-17)
My_Clock\clk_1Hz.fit.summary (595, 2009-11-17)
My_Clock\clk_1Hz.fit.rpt (109080, 2009-11-17)
My_Clock\clk_1Hz.sof (151050, 2009-11-17)
My_Clock\clk_1Hz.pof (524474, 2009-11-17)
My_Clock\clk_1Hz.asm.rpt (7397, 2009-11-17)
My_Clock\clk_1Hz.tan.summary (1310, 2009-11-17)
My_Clock\clk_1Hz.tan.rpt (108182, 2009-11-17)
My_Clock\clk_1Hz.dpf (239, 2009-11-17)
My_Clock\clk_1Hz.vhd.bak (6921, 2009-11-17)
My_Clock\clk_1Hz.vhd (7094, 2009-12-05)
My_Clock\counter.bdf (37036, 2009-11-17)
My_Clock\shift_8bit.bsf (1607, 2009-11-17)
My_Clock\shift_1B.bsf (2882, 2009-11-15)
My_Clock\conter6.bsf (1954, 2009-11-17)
My_Clock\shift_1byte.bsf (2885, 2009-11-17)
My_Clock\conter10.bsf (1955, 2009-11-17)
... ...
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