bram_delay
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1405KB
下载次数：71
上传日期：2009-12-09 11:19:29
上 传 者：
jadekung
说明： Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址
(Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file)
文件列表:
bram_delay\.lso (6, 2009-08-07)
bram_delay\blk_mem_gen_ds512.pdf (2107313, 2009-08-07)
bram_delay\blk_mem_gen_release_notes.txt (4492, 2009-08-07)
bram_delay\bram_16.asy (964, 2009-08-07)
bram_delay\bram_16.ngc (29501, 2009-08-07)
bram_delay\bram_16.sym (1705, 2009-08-07)
bram_delay\bram_16.v (4647, 2009-08-07)
bram_delay\bram_16.veo (3206, 2009-08-07)
bram_delay\bram_16.vhd (5415, 2009-08-07)
bram_delay\bram_16.vho (3815, 2009-08-07)
bram_delay\bram_16.xco (2118, 2009-08-07)
bram_delay\bram_16_blk_mem_gen_v2_4_xst_1.lso (18, 2009-08-07)
bram_delay\bram_16_blk_mem_gen_v2_4_xst_1_vhdl.prj (1865, 2009-08-07)
bram_delay\bram_16_flist.txt (218, 2009-08-07)
bram_delay\bram_16_xmdf.tcl (3192, 2009-08-07)
bram_delay\bram_delay.doc (31232, 2009-08-10)
bram_delay\bram_delay.ise (250615, 2009-08-31)
bram_delay\bram_delay.ise_ISE_Backup (250615, 2009-08-31)
bram_delay\bram_delay.prj (29, 2009-08-07)
bram_delay\bram_delay.restore (53355, 2009-08-31)
bram_delay\bram_delay.stx (782, 2009-08-07)
bram_delay\bram_delay.v (2024, 2009-08-13)
bram_delay\bram_delay.xst (78, 2009-08-07)
bram_delay\bram_delay_summary.html (2297, 2009-08-31)
bram_delay\isim\temp\hdllib.ref (342, 2009-08-13)
bram_delay\isim\temp\hdpdeps.ref (549, 2009-08-13)
bram_delay\isim\temp\vlg06\tb__bram__delay__v.bin (1999, 2009-08-13)
bram_delay\isim\temp\vlg08\bram__16.bin (7060, 2009-08-13)
bram_delay\isim\temp\vlg2D\glbl.bin (3401, 2009-08-13)
bram_delay\isim\temp\vlg48\bram__delay.bin (7263, 2009-08-13)
bram_delay\isim\work\bram__16\bram__16.h (944, 2009-08-07)
bram_delay\isim\work\bram__16\mingw\bram__16.obj (15051, 2009-08-07)
bram_delay\isim\work\bram__delay\bram__delay.h (1008, 2009-08-13)
bram_delay\isim\work\bram__delay\mingw\bram__delay.obj (32742, 2009-08-13)
bram_delay\isim\work\glbl\glbl.h (946, 2009-08-07)
bram_delay\isim\work\glbl\mingw\glbl.obj (25182, 2009-08-07)
bram_delay\isim\work\hdllib.ref (448, 2009-08-31)
bram_delay\isim\work\hdpdeps.ref (670, 2009-08-31)
bram_delay\isim\work\tb__bram__delay__v\mingw\tb__bram__delay__v.obj (27163, 2009-08-31)
... ...
The following files were generated for 'bram_16' in directory
G:\program\bram_delay:
bram_16.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
bram_16.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
bram_16.sym:
Please see the core data sheet.
bram_16.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
bram_16.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
bram_16.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
bram_16.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
bram_16.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
bram_16_blk_mem_gen_v2_4_xst_1_vhdl.prj:
Please see the core data sheet.
bram_16_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
bram_16_readme.txt:
Text file indicating the files generated and how they are used.
bram_16_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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