ddrsdram_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：734KB
下载次数：158
上传日期：2009-12-09 15:21:19
上 传 者：
chenshaohua9
说明： 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。
(Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.)
文件列表:
model\mt46v4m16.v (44955, 2000-03-29)
route\ddr_sdram.csf (10358, 2000-06-02)
route\ddr_sdram.esf (618, 2000-06-02)
route\ddr_sdram.psf (2443, 2000-06-02)
route\ddr_sdram.quartus (194, 2000-06-02)
route\ddr_sdram.vqm (595323, 2000-05-22)
route\pll1.v (4648, 2000-05-20)
simulation\ddr_compile_all.v (213, 2000-05-20)
simulation\ddr_sdram_tb.v (18362, 2000-05-19)
simulation\modelsim.ini (7728, 2000-05-21)
simulation\work\altclklock\verilog.psm (20672, 2000-05-21)
simulation\work\altclklock\_primary.dat (2333, 2000-05-21)
simulation\work\altclklock\_primary.vhd (899, 2000-05-21)
simulation\work\ddr_command\verilog.psm (46232, 2000-05-21)
simulation\work\ddr_command\_primary.dat (5126, 2000-05-21)
simulation\work\ddr_command\_primary.vhd (1327, 2000-05-21)
simulation\work\ddr_control_interface\verilog.psm (21720, 2000-05-21)
simulation\work\ddr_control_interface\_primary.dat (2785, 2000-05-21)
simulation\work\ddr_control_interface\_primary.vhd (1113, 2000-05-21)
simulation\work\ddr_data_path\verilog.psm (24088, 2000-05-21)
simulation\work\ddr_data_path\_primary.dat (3215, 2000-05-21)
simulation\work\ddr_data_path\_primary.vhd (817, 2000-05-21)
simulation\work\ddr_sdram\verilog.psm (28640, 2000-05-21)
simulation\work\ddr_sdram\_primary.dat (4552, 2000-05-21)
simulation\work\ddr_sdram\_primary.vhd (1085, 2000-05-21)
simulation\work\ddr_sdram_tb\verilog.psm (61744, 2000-05-21)
simulation\work\ddr_sdram_tb\_primary.dat (9399, 2000-05-21)
simulation\work\ddr_sdram_tb\_primary.vhd (102, 2000-05-21)
simulation\work\mt46v4m16\verilog.psm (232024, 2000-05-21)
simulation\work\mt46v4m16\_primary.dat (25110, 2000-05-21)
simulation\work\mt46v4m16\_primary.vhd (1174, 2000-05-21)
simulation\work\pll1\verilog.psm (4896, 2000-05-21)
simulation\work\pll1\_primary.dat (823, 2000-05-21)
simulation\work\pll1\_primary.vhd (256, 2000-05-21)
simulation\work\_info (1109, 2000-05-21)
source\altclklock.v (9281, 2000-05-20)
source\ddr_Command.v (16585, 2000-06-02)
source\ddr_control_interface.v (9424, 2000-06-02)
source\ddr_data_path.v (9440, 2000-05-23)
... ...
Directory: \simulation
This directory contains the verilog testbench and the modelsim ini file for the
DDR SDRAM controller reference design. The \work directory contains a precompiled
library of the complete design. In order to modify the design and re-simulate, simply
copy the source files from \source and \model into this directory and re-compile the
design.
近期下载者：
相关文件：
收藏者：