DDRSDRAM_VHDL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：866KB
下载次数：28
上传日期：2009-12-09 15:27:40
上 传 者：
chenshaohua9
说明： 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计
库函数；source包含vhdl源文件；synthesis包含工程的综合文件。
(Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.)
文件列表:
doc\ddr_sdram.pdf (472801, 2000-05-30)
model\mt46v4m16.vhd (43490, 1999-11-08)
model\mti_pkg.vhd (4932, 2000-08-14)
route\ddr_sdram.csf (10673, 2000-08-14)
route\ddr_sdram.esf (737, 2000-08-14)
route\ddr_sdram.quartus (193, 2000-08-14)
route\ddr_sdram.vqm (603177, 2000-06-30)
route\pll1.vhd (5081, 2000-06-29)
simulation\APEX20KE_MF.VHD (42715, 2000-06-29)
simulation\ddr_command.vhd (17418, 2000-08-14)
simulation\ddr_control_interface.vhd (9161, 2000-08-14)
simulation\ddr_data_path.vhd (9286, 2000-08-14)
simulation\ddr_sdram.vhd (18307, 2000-08-14)
simulation\ddr_sdram_tb.vhd (24245, 2000-08-14)
simulation\io_utils.vhd (8703, 1998-01-16)
simulation\lpm_pack.vhd (22051, 1999-10-22)
simulation\modelsim.ini (8116, 2000-08-14)
simulation\mt46v4m16.vhd (43490, 1999-11-08)
simulation\mti_pkg.vhd (4932, 2000-08-14)
simulation\pll1.vhd (5081, 2000-06-29)
simulation\stdlogar.vhd (68654, 1998-01-16)
simulation\util1164.vhd (3310, 1998-01-16)
simulation\wave.do (5967, 2000-08-14)
simulation\work\altcam\behave.dat (7970, 2000-08-14)
simulation\work\altcam\behave.psm (69568, 2000-08-14)
simulation\work\altcam\_primary.dat (5972, 2000-08-14)
simulation\work\altclklock\behavior.dat (2016, 2000-08-14)
simulation\work\altclklock\behavior.psm (12360, 2000-08-14)
simulation\work\altclklock\_primary.dat (799, 2000-08-14)
simulation\work\altlvds_rx\behavior.dat (3122, 2000-08-14)
simulation\work\altlvds_rx\behavior.psm (14800, 2000-08-14)
simulation\work\altlvds_rx\_primary.dat (563, 2000-08-14)
simulation\work\altlvds_tx\behavior.dat (1868, 2000-08-14)
simulation\work\altlvds_tx\behavior.psm (9720, 2000-08-14)
simulation\work\altlvds_tx\_primary.dat (598, 2000-08-14)
simulation\work\command\rtl.dat (4679, 2000-06-28)
simulation\work\command\rtl.psm (32120, 2000-06-28)
simulation\work\command\_primary.dat (1072, 2000-06-28)
simulation\work\control_interface\rtl.dat (2240, 2000-06-28)
... ...
Directory: \simulation
This directory contains the vhdl testbench, associated files and the modelsim ini file for the
DDR SDRAM controller reference design. The \work directory contains a precompiled
library of the complete design. In order to modify the design and re-simulate, simply
copy the source files from \source and \model into this directory and re-compile the
design.
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