axi_ipif_v2.3.zip - The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced
eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point bidirectional interface between a user Intellectual Property (IP) core and the AXI interconnect.,2017-08-08 18:54:28,下载10次
Z-turn-examples-master.zip - # Z-turn-examples
The repository with my simple Z-turn examples, to be used as templates for more serious projects.
Please note, that the Buildroot configuration in my designs sets the root password to "test".
Setting the password is necessary to allow SSH login to the Z-Turn board. Of course you can easily modify that
(either to set a better password or to delete the password at all).,2017-08-08 18:44:17,下载5次
XilinxVirtualCable-master.zip - Xilinx虚拟连接，这是一种基于TCP/IP协议的通信技术，以实现JTAG功能，通过这样的连接，可以访问开发的FPGA或者SOC，而不需要通过传统的JTAG电缆。,2017-08-08 18:41:25,下载24次
VB_60_LAN_Sockets.zip - VB源码实现网口控制安捷伦N6700A仪器，ZIP包中包含工程等多个文件,2012-03-04 18:37:23,下载35次
verilog_8524_ip.rar - 用verilog语言编写的8254代码，实现8254功能,2012-02-08 21:43:10,下载22次
FPGA_ARINC_429_design.rar - 机载数据总线ARINC 429在当代的运输机和相当数量的民用客机中有着广泛的应用。目前国内的专用ARINC 429信号处理芯片一般路数有限,要实现多通道的信息处理,就需要多块类似的芯片,从而体积就会变的比较庞大,非常不灵活。,因此利用FPGA和DSP相结合,设计和研制的ARINC 429总线信号处理板,成为目前飞机机载总线接口研究的重点,具有非常重要的现实意义和应用前景。
,2012-02-08 21:40:01,下载42次
ddr_verilog_xilinx.zip - DDR_verilog_xilinx 原语,2009-01-13 18:53:14,下载12次