reset_generate.zip - -- reset_leng is length of reset signal ( remultiple of clk cycle)
-- reset_generate_time is multiple of clk cycle after system OK
-- count_leng is length of count
,2009-03-26 05:26:29,下载2次
ethernet.tar.gz - VHDL MAC wishbone VHDL MAC wishbone,2009-03-10 22:38:46,下载38次