STUDENTS_SCORE.zip - Specifications
1. Top module name :SS (File name : SS.v)
2. Input pins: CLK, RESET, IN_VALID, INPUT [6:0]
- 2 -
3. Output pins: OUT_VALID, OUTPUT [6:0]
4. Synchronous active high RESET is used, and no latch design is allowed.
5. All input signals will be changed at negative edge of clock. IN_VALID is high
when INPUT [6:0] is valid.
6. OUT_VALID will be high when OUTPUT is valid, and test pattern will compare
your output signals to the correct answer.
7. The valid output sequence must be continuous without any interruption.
8. Input delay and output delay are 0.5*clock period.
9. After synthesis, check the “SS.area” and “SS.timing” in the folder “Report”.
The area report is valid only when the slack in the end of SS.timing is
non-negative.
10. All outputs are sampled at negative clock edge.
11. The clock period is 5 ns.
12. The output loading is 0.05.,2010-01-14 18:37:22,下载1次
matrix_multiplier_with_memory.zip - A matrix is a rectangular table of elements,which can be any number or abstract quantities that can be added and multiplied. Matrix multiplication is the operation of multiplying a matrix with a scalar or another matrix, which is simple fuction widely used to solve mathematical question in EECS field.,2010-01-14 18:17:50,下载24次
convolution_calculator_4_bits.zip - convolution is important and is widely used in digital signal processing.For example, in LTI system.
Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.,2010-01-14 17:54:47,下载13次
TIC_TAC_game_gate_level.zip - Tic Tac Game is a classic game. Two players are using code-named “0” and “1”, fill in rotation in TICTACTOEMIDLET. If any player gates the first straight line will win, and if nobody is successful then the tie
1. Top module name： TT (Filename: TT.v)
2. Input pins: IN_AtoI [8:0]
3. Output pins: OUT [1:0]
4. All of the input are 1-bit numbers.
5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design.
It can only use not, and, nand, or, nor, xor, xnor logic gates.
It can only use up to 4-input logic gates.,2010-01-14 17:46:56,下载3次
Long_shift_gate_level.zip - 1.
Top module name : SHIFTER (File name : SHIFTER.v)
2.
Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3.
Output pins: OUT [15:0].
4.
Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
5.
The SHIFT signal describes the shift number. The shift range is 0 to 15.
6.
When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left.
7.
When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low.
8.
You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
9.
The logarithmic shifter is based on a staged approach (powers of 2). A simple architecture is described as Figure 1.,2010-01-14 17:43:55,下载3次