RTL_Compiler_synthesis.pdf.zip - HOW TO SYNTHESIZE VERILOG CODE USING RTL COMPILER
This tutorial explains how to synthesize a verilog code using RTL Compiler. In order to do so,
let’s consider the verilog codes below.,2014-02-06 19:52:36,下载4次
The_first_CoOS_program.zip - INTRODUCTION
The course program on Verilog HDL Basics is designed for undergraduate education on “VLSI Design” specialization. The course duration is 64 hours, lectures volume is 32 hours, and laboratory works are 32 hours.
COURSE GOALS AND OBJECTIVES
The goal of the course is to teach future designers the principles of Verilog HDL based design, as well as to promote an interest in life-long learning together with the ability to advance professionally.,2014-02-06 19:49:16,下载3次
Testing-an-S-Box-for-Cryptographic-Use.pdf.zip - Testing an S-Box for Cryptographic Use
Generally, one faces two type of problems related to the selection of
an s-box (substitution box/function) before its cryptographic use can be
considered secure. First one is how to design (or search) a good s-box
and second one is how to verify a given s-box is indeed a good one in
a sense of meeting its requirements. The requirements contain the types
and quantitative values of desired properties for an s-box.,2014-02-06 19:29:40,下载4次
thesis-235.pdf.zip - Cryptographic algorithms are designed to protect data or communication in
the presence of an attacker. If these algorithms make use of a secret key, then
their security relies on the secrecy of the key. Hence, the primary objective
of an attacker typically is to extract the key. In a traditional black-box
environment, the attacker has only access to the inputs and outputs of a
cryptographic algorithm.,2014-02-06 19:25:56,下载6次
an503.zip - OFDM transmitter design and implementation,2010-04-28 22:42:16,下载4次