lowpowerfir.gz - This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system.
The power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design. ,2010-07-25 16:55:31,下载7次
viterbi.gz - This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.,2010-07-25 16:50:28,下载42次
cFFT.rar.gz - CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and
a configurable number of sample points in the FFT.
Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the
CFFT core to be different from the standard FFT algorithm. This variation in gain
is not important for orthogonal frequency division modulation (OFDM) and demodulation.
The gain can be corrected, to that of a conventional FFT, by applying a constant
multiplying factor.
,2010-07-25 16:43:50,下载74次
matrix.rar.gz - 3x3 matrix implementation in VHDL,2010-07-25 16:40:52,下载8次
256fft.rar.gz - • 256 -point radix-8 FFT.
• Forward and inverse FFT.
• Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from
input to output is equal to 580 clock cycles (839 clock cycles when the direct output data
order), simultaneous loading/downloading supported.
• Input data, output data, and coefficient widths are parametrizable in range 8 to 16 and
more.
• Two and three data buffers are selected.
• FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at 250
MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle, respectively.
• FFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1652 CLB slices, 4
DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 670 CLB slices 4
DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are
implemented on the distributed RAM.
,2010-07-25 16:35:36,下载186次
NCLPROJECT.rar - The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration.
,2010-07-24 14:05:16,下载5次