07.zip - Top quality code written in VHDL ,2015-11-27 14:08:19,下载1次
ASK_implement.rar - Implementation of ASK techniqe as digital modulation tchnique using Verilog,2015-10-28 16:19:01,下载2次
CDMA_ver.rar - Iplementation of CDMA reciever and Transmitter using VHDL and Verilog Coding,2015-10-28 16:17:17,下载11次
3-ici-diminution.rar - In a rapidly fading environment in high data rate wireless communication systems the orthogonality of OFDM sub carrier signals destroyed and this phenomenon potentially results in Inter carrier interference (ICI).The novel contribution of the paper is that, the effects of ICI have been analyzed and solutions to ICI diminution have been presented in different frequency offset values such as 0.5,0.15 and 0.30 . The first method is a self-cancellation scheme, in which redundant data is transmitted onto adjacent subcarriers such that the ICI between adjacent sub carriers cancels out at the receiver. The other technique the Extended Kalman Filter (EKF) method statistically estimate the frequency offset and correct the offset using the estimated value at the receiver,2015-10-28 16:13:47,下载19次
Dual-Band-Slotted-Microstrip-Patch-Antenna-with-D - This microstrip patch antenna for dual band frequency is designed with the help of defected ground structure to obtain a patch antenna with small dimensions and sufficient bandwidth as compared to conventional patch antenna .The effect of defected ground structure is shown in this paper. This antenna has dual bands at frequencies around 3.75GHZ and 6.5GHz.,2015-10-28 16:10:25,下载1次
184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ- - In this system, we discuss the architecture, design, and testing of the
first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid
single flux quantum adder implemented using the ISTEC 10 kA/cm
2ADP2.1 fabrication process. Compared to the Kogge–Stone adder, our
parallel-prefix sparse-tree adder has better energy efficiency with
significantly reduced complexity (at the expense of latency) and almost no
decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc
and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area
of 8.5 mm 2. It is designed for the target operation frequency of 30 GHz
with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder
chip was fabricated and successfully tested at low frequency for all test
patterns with measured bias margins of +9.8 /− 10.7 .,2015-10-28 16:05:35,下载1次