wb_sdram_ctrl.tar.gz - Generic Wishbone R3 compliant SDRAM controller written in Verilog,2014-12-20 04:43:54,下载9次
verilog-arbiter.tar.gz - Verilog arbitrator for Wishbone R3 compliant bus,2014-12-20 04:42:21,下载2次
or1200.tar.gz - OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders,2014-12-20 04:40:23,下载7次
APB_slave.zip - APB slave template for AMBA bus written in Verilog,2014-12-20 04:34:29,下载44次
V2.tar.gz - SDIO slave, written in verilog, does not support SPI mode.,2014-12-20 04:30:14,下载85次