ofdm.rar - There is a simulation of Orthogonal Frequency Division Multiplexing (OFDM) in by multipath fading channels.
,2015-03-22 02:49:22,下载3次
jpg.rar - The aim of this short workshop is to demonstrate the effectiveness of the JPEG encoding/decoding process using test data and test images. As explained in the lectures the major elements of the JPEG encoding process are the DCT, the non-uniform Quantisation matrix and variable run-length encoding.
Building an emulator of the JPEG encoding and decoding algorithm may appear a daunting task, but Matlab is well suited to such coding.,2015-03-22 02:46:18,下载2次
sayeh.zip - The SAYEH (Simple Architecture, Yet Enough Hardware) is a processor architecture that has been developed by Navabi in [1] for experimental and teaching purposes. As the name implies it is a “simple” architecture but contains sufficient hardware to make it a challenge. In this and the following workshops we will be developing this processor architecture to practice our skills in developing VHDL code which will be useful in later laboratories when we will be building more complex structures. Unfortunately the SAYEH code provided by Navabi is written in Verilog, we will be translating it to VHDL.,2015-03-22 02:43:47,下载5次
add.rar - The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1 components.,2015-03-22 02:42:24,下载1次
vga.zip - vga
This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.,2015-03-22 02:26:44,下载1次