DSP48E1_ComplexMul.zip - This module does Complex multiplication based on Xilinx DSP48E1 dsp block. Proved on xilinx Virtex 6 Devices,2017-12-30 04:50:21,下载5次
RGMII_TRANSMITTER.zip - This module converts 8 bit SDR flow to 4 bit DDR RGMII flow, proved on Altera Cyclone 3 devices.,2017-12-30 04:37:43,下载25次
RGMII_RECEIVER.zip - This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.,2017-12-30 04:36:09,下载21次
Up_Down_Counter v1.0.zip - FPGA Up/Down couner Module,2017-12-30 04:28:16,下载1次
Quadrature_MACx42_AvalonSt_Input v1.0.zip - This module does Complex MAC based on Altera Stratix 2 DSP Blocks.,2017-12-30 04:24:28,下载2次
ACCx42_AvalonST_Input.zip - This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices,2017-12-30 03:37:29,下载1次
ACC_CarryIn_CarryOut.zip - This module does Accumulate operation used in dsp. Tested on fpga.,2017-12-30 02:04:21,下载1次
EthCRC32.zip - This module calculates ethernet crc32 on fpga using table method,2017-12-29 17:56:23,下载7次