YUV2RGB.zip - This design example implements a basic YUV422 to RGB888 colour space conversion.
The component in this example reads a single YUV422 word (representing two YUV
pixels) and emits two RGB888 words (representing two RGB pixels).
The testbench reads image_in.bmp (an RGB encoded bitmap), converts the data to
YUV422 format, then passes the YUV422 data to the component to convert back to
RGB format. The resulting RGB image (which has undergone two colour space
transformations: RGB888 -> YUV422 -> RGB888) is emitted to image_out.bmp. For
the sample image provided, the output can be compared to image_out.bmp.golden
to verify correctness.,2018-10-26 09:59:39,下载0次
image_downsample.zip - This design example implements an image downsampling algorithm to scale an
image to a smaller size using bilinear interpolation.
The testbench reads an image from test.bmp, emits a scaled down version to
downsampled.bmp, and compares the results to a golden reference image in
expected.bmp.,2018-10-26 09:57:31,下载0次
counter.zip - This design example demonstrates a trivial counter. The component
initializes a static counter to 0, and increments on every call.,2018-10-26 09:56:06,下载0次
sysgen_demos.zip - System Generator for DSP is a design tool in the Vivado Design Suite that enables you to use the MathWorks model-based Simulink design environmentfor FPGA design.,2018-10-26 09:49:42,下载6次
Vivado_Tutorial.zip - This is a simple IP Integrator based Zynq design. A Bus Functional Model Simulation can be run on this design.,2018-10-26 09:44:18,下载4次