daluakki

积分:211
上传文件:8
下载次数:129
注册日期:2016-09-13 19:19:31

上传列表
Adder-Designs-using-Reversible-Logic-Gates.rar - REVERSIBLE LOGIC BASED ADDERS DOCUMENTATION,2016-09-13 20:07:50,下载6次
brent_kung_add.rar - BRENT KUNG ADDER CODE,2016-09-13 20:05:22,下载5次
CRC-DOCUMENTATION.rar - CYCLIC REDUNDACY CHECK DOCUMENTATION,2016-09-13 19:59:46,下载1次
binary-squarer.rar - BINARARY SQURING CIRCUIT DOCUMENTATION,2016-09-13 19:58:02,下载2次
cbl-documentation.rar - COMMON BOOLEAN LOGIC DOCUMENTATION,2016-09-13 19:55:46,下载1次
bcd-doc.rar - BINARY TO BCD DOCUMENT,2016-09-13 19:50:34,下载1次
MAC-DATA.zip - MAC UNIT DOCUMENTATION,2016-09-13 19:45:02,下载3次
FIFO-DOCUMENATATION.zip - DOCUMENTATION OF FIFO,2016-09-13 19:42:52,下载3次

近期下载
c499.rar - sec code 电路,用于纠错检错和错误恢复的功能,verilog描述。
multiply.rar - 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.
code.rar - Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage.
50846288C.rar - verilog 硬件编程实现bpsk调制
MD5.zip - 哈希算法FPGA实现代码,采用MD5算法,并给出了仿真波形。
MD5(verilog).rar - MD5算法的verilog实现,同时包含有testbench。
save_adder.rar - implement of carry save adder with verilog
serial_adder.rar - This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
urunn_length_s.rar - <p>用verilog 开发应用于图像压缩编码中使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。</p>
wallace-tree-multiplier.rar - 关于fpga乘法器的一种算法,一种wallace树压缩器硬件结构的实现
CSA.tar.gz - A Carry Select Adder.
galois_lfsr_latest.tar.gz - GALOIS FIELD POLYNOMIAL BASED LFSR
Viterbi_algorithm_VeeRen.rar - Viterbi algorithm using Verilog
viterbi.rar - verilog code for viterbi encoder and decoder
vertibi.rar - (2,1,7)viterbi convolutional code encoding, decoding, debugging through, you can directly use
verilog-juanjima.rar - 卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog  HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快
viterbi.gz - This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
VDK9R12.rar - viterbi译码器(2.1.7),里面什么都有,测试模块,编码模块和译码模块
viterbi.rar - verilog程序,实现了(2,1,4)卷积码编码,和基于回溯算法的维特比译码器
Viterbi_v.rar - Viterbi算法的Verilog源代码。

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