注册日期:2020-01-14 16:24:57

at7_ex24.rar - Different switch states of the DIP switch control the 7-inch LCD screen to display moving 0V, 3.3V, square wave, triangle wave, sine wave or ADC to collect data.,2020-01-14 16:50:15,下载0次
at7_ex11.rar - The ultimate result of ultrasonic ranging shows that every 100ms, a high-pulse excitation of 10us required by an ultrasonic ranging module is generated, and the digitally displayed decimal distance data (unit mm) is displayed in decimal data using a digital tube.,2020-01-14 16:45:25,下载0次
at7_ex20.rar - 5 channels of data + 1 channel of clock for LVDS data transmission and reception, to achieve cyclic transmission of fixed data, LVDS transmission parallel conversion, LVDS reception serial conversion, bit alignment processing and effective data frame analysis.,2020-01-14 16:41:57,下载0次
at7_ex17.rar - This example instantiates the DDR3 controller IP core module provided in Xilinx Vivado to achieve basic DDR3 reader operation. The simulation of the DDR3 IP core is achieved through an example of a test script automatically generated by the IP core.,2020-01-14 16:39:36,下载1次

Framer.rar - ISE平台下的verilog的QC-LDPC编码,经仿真没有问题
verilog_rtl.rar - 关于LDPC解码的verilog程序,包含设计代码和验证环境
ldpc576.zip - 基于wimax协议的低密度奇偶校验码LDPC的VERILOG实现,亲测可用。
Ive_abd_code.rar - 最近在做毕设,ldpc码的编解码实现,这个是verilog实现,
QC_LDPC译码器的FPGA设计.zip - LDPC码的FPGA实现,用verilog语言编写