The following files were generated for 'image_rom' in directory D:\Xilinx91i\project\show_image2: image_rom.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. image_rom.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. image_rom.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. image_rom.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. image_rom.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. image_rom.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. image_rom.sym: Please see the core data sheet. image_rom.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. image_rom.xco: CORE Generator input file containing the parameters used to regenerate a core. image_rom_xmdf.tcl: Please see the core data sheet. image_rom_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. image_rom_readme.txt: Text file indicating the files generated and how they are used. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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