xapp460
所属分类:VHDL/FPGA/Verilog
开发工具:Unix_Linux
文件大小:92KB
下载次数:124
上传日期:2009-07-26 11:02:40
上 传 者:
xm11111
说明: xilinx hdmi tx rx verilog code
文件列表:
xapp460\dvi_demo (0, 2008-07-25)
xapp460\dvi_demo\rtl (0, 2008-07-25)
xapp460\dvi_demo\rtl\rx (0, 2008-07-25)
xapp460\dvi_demo\rtl\rx\chnlbond.v (5887, 2008-07-24)
xapp460\dvi_demo\rtl\rx\dcminit.v (4701, 2008-07-24)
xapp460\dvi_demo\rtl\rx\decode.v (10479, 2008-07-24)
xapp460\dvi_demo\rtl\rx\dvi_decoder.v (6242, 2008-07-24)
xapp460\dvi_demo\rtl\rx\phsaligner.v (18475, 2008-07-24)
xapp460\dvi_demo\rtl\rx\tmds_1c_1to10.v (8751, 2008-07-24)
xapp460\dvi_demo\rtl\tx (0, 2008-07-25)
xapp460\dvi_demo\rtl\tx\dvi_encoder.v (3959, 2008-07-24)
xapp460\dvi_demo\rtl\tx\encode.v (7601, 2008-07-24)
xapp460\dvi_demo\rtl\tx\serdes_4b_10to1_fifo.v (14335, 2008-07-24)
xapp460\dvi_demo\rtl\common (0, 2008-07-25)
xapp460\dvi_demo\rtl\common\DRAM16XN.v (1667, 2008-07-24)
xapp460\dvi_demo\rtl\common\timing.v (8425, 2008-07-24)
xapp460\dvi_demo\rtl\common\synchro.v (3890, 2008-07-24)
xapp460\dvi_demo\rtl\common\debnce.v (3700, 2008-07-24)
xapp460\dvi_demo\rtl\common\hdclrbar.v (17508, 2008-07-24)
xapp460\dvi_demo\rtl\logofly (0, 2008-07-25)
xapp460\dvi_demo\rtl\logofly\autopilot.v (10272, 2008-07-24)
xapp460\dvi_demo\rtl\logofly\cursor_pair.v (5809, 2008-07-24)
xapp460\dvi_demo\rtl\logofly\s3a_logo.v (36831, 2008-07-24)
xapp460\dvi_demo\rtl\dvi_demo.v (13116, 2008-07-24)
xapp460\hdmi_demo (0, 2008-07-25)
xapp460\hdmi_demo\rtl (0, 2008-07-25)
xapp460\hdmi_demo\rtl\hdmi_demo.v (18216, 2008-07-24)
xapp460\hdmi_demo\rtl\common (0, 2008-07-25)
xapp460\hdmi_demo\rtl\common\DRAM16XN.v (1667, 2008-07-24)
xapp460\hdmi_demo\rtl\common\timing.v (8425, 2008-07-24)
xapp460\hdmi_demo\rtl\common\synchro.v (3890, 2008-07-24)
xapp460\hdmi_demo\rtl\common\debnce.v (3700, 2008-07-24)
xapp460\hdmi_demo\rtl\common\srldelay.v (2931, 2008-07-24)
xapp460\hdmi_demo\rtl\logofly (0, 2008-07-25)
xapp460\hdmi_demo\rtl\logofly\autopilot.v (10272, 2008-07-24)
xapp460\hdmi_demo\rtl\logofly\cursor_pair.v (5809, 2008-07-24)
xapp460\hdmi_demo\rtl\logofly\s3a_logo.v (36831, 2008-07-24)
xapp460\hdmi_demo\rtl\rx (0, 2008-07-25)
xapp460\hdmi_demo\rtl\rx\chnlbond.v (5887, 2008-07-24)
... ...
*******************************************************************************
** 2006-2008 Xilinx, Inc. All Rights Reserved.
** Confidential and proprietary information of Xilinx, Inc.
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/ Version: 1.0
** \ \ Filename:
** / / Date Last Modified:
** /___/ /\ Date Created:
** \ \ / \
** \___\/\___\
**
** Device: Spartan-3A, Spartan-3AN and Spartan-3ADSP
** Purpose:
** Reference: XAPP460 Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
** Revision History:
**
*******************************************************************************
**
** Disclaimer:
**
** Xilinx licenses this Design to you "AS-IS" with no warranty of any kind.
** Xilinx does not warrant that the functions contained in the Design will
** meet your requirements,that the Design will operate uninterrupted or be
** error-free, or that errors or bugs in the Design will be corrected.
** Xilinx makes no warranties or representations in regard to the results
** obtained from your use of the Design with respect to accuracy, reliability,
** or otherwise.
**
** XILINX MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS OR IMPLIED,
** STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES
** OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE.
** IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR FOR
** ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING FROM
** YOUR USE OF THIS DESIGN.
*******************************************************************************
This readme describes how to use the files that come with XAPP460.
*******************************************************************************
** IMPORTANT NOTES **
1) All design files have been hardware tested using a Xilinx internal TMDS characterization
board.
********************************************************************************
To incorporate the insert name here module into an ISE design project:
Verilog flow:
1) Create an ISE project using appropriate design files discussed in the xapp460.pdf.
2) Create a Xilinx UCF file as discussed in the xapp460.pdf.
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