rtl
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：40KB
下载次数：44
上传日期：2010-01-04 11:48:50
上 传 者：
jh3mail
说明： 基于脉动结构的有限域乘法器，verilog代码
(Based on the pulse of the structure of finite field multipliers, verilog code)
文件列表:
rtl\cell1.v (582, 2010-01-04)
rtl\cell2.v (518, 2010-01-04)
rtl\DFF1.v (290, 2010-01-04)
rtl\DFF16.V (321, 2010-01-04)
rtl\DFF32.v (326, 2010-01-04)
rtl\DFF8.V (312, 2010-01-04)
rtl\MUX.v (247, 2010-01-04)
rtl\PE16.V (68692, 2010-01-04)
rtl\PE32.V (240599, 2010-01-04)
rtl\PE8.V (22919, 2010-01-04)
rtl\tb_TOP32.v (1719, 2010-01-04)
rtl\TOP16.V (5306, 2010-01-04)
rtl\TOP32.v (3026, 2010-01-04)
rtl\TOP8.V (18817, 2010-01-04)
rtl (0, 2010-01-04)
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