LIP1742CORE_sdio_rx_fsm

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:254KB
下载次数:36
上传日期:2010-11-14 01:17:31
上 传 者joneychen12
说明:  Verilog SDIO RX FSM module

文件列表:
FSM_1\.untf (0, 2007-07-13)
FSM_1\automake.log (0, 2007-07-13)
FSM_1\FSM_1.dhp (983, 2007-07-13)
FSM_1\FSM_1.ise (4483, 2007-07-13)
FSM_1\FSM_1.ise_ISE_Backup (4483, 2007-07-13)
FSM_1\Project.dhp (982, 2007-07-13)
FSM_1\sdio_rx_fsm.bld (721, 2007-07-13)
FSM_1\sdio_rx_fsm.cel (0, 2007-07-13)
FSM_1\sdio_rx_fsm.cmd_log (272, 2007-07-13)
FSM_1\sdio_rx_fsm.lso (6, 2007-07-13)
FSM_1\sdio_rx_fsm.ngc (102676, 2007-07-13)
FSM_1\sdio_rx_fsm.ngd (181287, 2007-07-13)
FSM_1\sdio_rx_fsm.ngr (112848, 2007-07-13)
FSM_1\sdio_rx_fsm.prj (30, 2007-07-13)
FSM_1\sdio_rx_fsm.stx (0, 2007-07-13)
FSM_1\sdio_rx_fsm.syr (21736, 2007-07-13)
FSM_1\sdio_rx_fsm.ucf (0, 1980-01-01)
FSM_1\sdio_rx_fsm.v (35428, 2007-07-13)
FSM_1\sdio_rx_fsm_summary.html (3143, 2007-07-13)
FSM_1\sdio_rx_fsm_vhdl.prj (0, 2007-07-13)
FSM_1\__projnav.log (12446, 2007-07-13)
FSM_1\__projnav\ednTOngd_tcl.rsp (54, 2007-07-13)
FSM_1\__projnav\FSM_1.gfl (636, 2007-07-13)
FSM_1\__projnav\FSM_1_flowplus.gfl (125, 2007-07-13)
FSM_1\__projnav\parentCreateTimingConstraintsApp_tcl.rsp (11, 2007-07-13)
FSM_1\__projnav\runXst_tcl.rsp (39, 2007-07-13)
FSM_1\__projnav\sdio_rx_fsm.xst (1111, 2007-07-13)
FSM_1\__projnav\sumrpt_tcl.rsp (18, 2007-07-13)
FSM_1\_ngo\netlist.lst (127, 2007-07-13)
FSM_1\xst\work\hdllib.ref (70, 2007-07-13)
FSM_1\xst\work\vlg09\sdio__rx__fsm.bin (78462, 2007-07-13)
LIP1742COR_sdio_rx_fsm_1.doc (132608, 2007-07-13)
LIP1742CORE_sdio_rx_fsm.doc (155648, 2007-07-02)
sdio_rx_fsm.v (35428, 2007-01-03)
FSM_1\xst\dump.xst\sdio_rx_fsm.prj\ngx\opt (0, 2010-09-19)
FSM_1\xst\dump.xst\sdio_rx_fsm.prj\ngx\notopt (0, 2010-09-19)
FSM_1\xst\dump.xst\sdio_rx_fsm.prj\ngx (0, 2010-09-19)
FSM_1\xst\work\vlg09 (0, 2010-09-19)
FSM_1\xst\dump.xst\sdio_rx_fsm.prj (0, 2010-09-19)
FSM_1\xst\work (0, 2010-09-19)
... ...

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