fir_compiler
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2087KB
下载次数：51
上传日期：2010-11-19 21:51:50
上 传 者：
sagillqq342
说明： FIR编译器。自动生成具有用户自定参数的FIR滤波器。
在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。
(FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl code is generated by the head of the document there was a generous definition, self-inspection.)
文件列表:
fir_compiler\doc\fir电路设计报告v01.doc (136704, 2009-09-03)
fir_compiler\doc\~$r电路设计报告v01.doc (162, 2009-09-02)
fir_compiler\doc\~WRL0003.tmp (215552, 2009-08-26)
fir_compiler\doc\~WRL0005.tmp (215552, 2009-09-02)
fir_compiler\doc\~WRL0730.tmp (185856, 2009-09-02)
fir_compiler\doc\~WRL3694.tmp (181248, 2009-09-02)
fir_compiler\doc\~WRL3859.tmp (193024, 2009-09-02)
fir_compiler\hdl\sim\fir_tb.cr.mti (1131, 2009-09-03)
fir_compiler\hdl\sim\fir_tb.mpf (21525, 2009-09-03)
fir_compiler\hdl\sim\in.dat (43340, 2009-09-03)
fir_compiler\hdl\sim\modelsim.tcl (1135, 2009-09-03)
fir_compiler\hdl\sim\out_cmp.dat (45155, 2009-09-03)
fir_compiler\hdl\sim\RTLOutDump.m (25357, 2009-09-03)
fir_compiler\hdl\sim\stim_def.v (448, 2009-09-03)
fir_compiler\hdl\sim\timescale.v (207, 2006-12-05)
fir_compiler\hdl\sim\vsim.wlf (2514944, 2009-09-02)
fir_compiler\hdl\sim\work\compare\verilog.asm (16670, 2009-09-03)
fir_compiler\hdl\sim\work\compare\_primary.dat (1197, 2009-09-03)
fir_compiler\hdl\sim\work\compare\_primary.vhd (368, 2009-09-03)
fir_compiler\hdl\sim\work\compare@out\verilog.asm (16046, 2009-09-03)
fir_compiler\hdl\sim\work\compare@out\_primary.dat (1149, 2009-09-03)
fir_compiler\hdl\sim\work\compare@out\_primary.vhd (374, 2009-09-03)
fir_compiler\hdl\sim\work\crom\verilog.asm (10343, 2009-09-03)
fir_compiler\hdl\sim\work\crom\_primary.dat (2740, 2009-09-03)
fir_compiler\hdl\sim\work\crom\_primary.vhd (251, 2009-09-03)
fir_compiler\hdl\sim\work\dpram\verilog.asm (14825, 2009-09-03)
fir_compiler\hdl\sim\work\dpram\_primary.dat (948, 2009-09-03)
fir_compiler\hdl\sim\work\dpram\_primary.vhd (554, 2009-09-03)
fir_compiler\hdl\sim\work\fir\verilog.asm (13435, 2009-09-03)
fir_compiler\hdl\sim\work\fir\_primary.dat (1587, 2009-09-03)
fir_compiler\hdl\sim\work\fir\_primary.vhd (616, 2009-09-03)
fir_compiler\hdl\sim\work\harness_filter\verilog.asm (9161, 2009-09-03)
fir_compiler\hdl\sim\work\harness_filter\_primary.dat (1055, 2009-09-03)
fir_compiler\hdl\sim\work\harness_filter\_primary.vhd (433, 2009-09-03)
fir_compiler\hdl\sim\work\loop_ctr\verilog.asm (30740, 2009-09-03)
fir_compiler\hdl\sim\work\loop_ctr\_primary.dat (2119, 2009-09-03)
fir_compiler\hdl\sim\work\loop_ctr\_primary.vhd (948, 2009-09-03)
fir_compiler\hdl\sim\work\pe\verilog.asm (21277, 2009-09-03)
fir_compiler\hdl\sim\work\pe\_primary.dat (1471, 2009-09-03)
fir_compiler\hdl\sim\work\pe\_primary.vhd (584, 2009-09-03)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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