文件列表:

sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7.edn (20831, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7.ngo (6842, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.edn (25389, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.ngo (8864, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.edn (36941, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.ngo (15463, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.edn (23844, 2011-04-27)
sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.ngo (8195, 2011-04-27)
sobel\binary_counter_virtex4_7_0_8c95a38a32cd3add.edn (20435, 2011-04-27)
sobel\binary_counter_virtex4_7_0_8c95a38a32cd3add.ngo (6546, 2011-04-27)
sobel\bmg_24_vx4_e54e5a776fc5110c.mif (40960, 2011-04-27)
sobel\bmg_24_vx4_e54e5a776fc5110c.ngc (25189, 2011-04-27)
sobel\globals (1582, 2011-04-27)
sobel\hdlFiles (30, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\verilog.asm (9648, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\verilog.rw (3337, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\_primary.dat (2072, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\_primary.dbs (816, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\_primary.vhd (438, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7 (0, 2011-05-10)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14\verilog.asm (9648, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14\verilog.rw (3337, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14\_primary.dat (2072, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14\_primary.dbs (816, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14\_primary.vhd (441, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_a05976c5f0c94e14 (0, 2011-05-10)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592\verilog.asm (8936, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592\verilog.rw (2873, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592\_primary.dat (2034, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592\_primary.dbs (561, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592\_primary.vhd (355, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_ca4e72d019e5d592 (0, 2011-05-10)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538\verilog.asm (9648, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538\verilog.rw (3337, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538\_primary.dat (2072, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538\_primary.dbs (816, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538\_primary.vhd (441, 2011-04-27)
sobel\modelsim\sobel\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538 (0, 2011-05-10)
sobel\modelsim\sobel\align_input\verilog.asm (13088, 2011-04-27)
sobel\modelsim\sobel\align_input\verilog.rw (2228, 2011-04-27)
... ...

The following files were generated for 'bmg_24_vx4_e54e5a776fc5110c' in directory .\: bmg_24_vx4_e54e5a776fc5110c.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. bmg_24_vx4_e54e5a776fc5110c.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. bmg_24_vx4_e54e5a776fc5110c.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. bmg_24_vx4_e54e5a776fc5110c.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. bmg_24_vx4_e54e5a776fc5110c.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. bmg_24_vx4_e54e5a776fc5110c.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. bmg_24_vx4_e54e5a776fc5110c.xco: CORE Generator input file containing the parameters used to regenerate a core. bmg_24_vx4_e54e5a776fc5110c_blk_mem_gen_v2_4_xst_1.ndf: Optional output file produced for cores that generate NGC files. The NDF files allow third party synthesis tools to infer resource utilization and timing from the NGC files associated with these new cores. bmg_24_vx4_e54e5a776fc5110c_blk_mem_gen_v2_4_xst_1.ngc_xst.xrpt: Please see the core data sheet. bmg_24_vx4_e54e5a776fc5110c_blk_mem_gen_v2_4_xst_1_vhdl.prj: Please see the core data sheet. bmg_24_vx4_e54e5a776fc5110c_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. bmg_24_vx4_e54e5a776fc5110c_readme.txt: Text file indicating the files generated and how they are used. bmg_24_vx4_e54e5a776fc5110c_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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