spi_controller
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：481KB
下载次数：170
上传日期：2011-08-11 16:00:27
上 传 者：
418478935
说明： SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。
(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)
文件列表:
spi_controller\bench.vcd (242571, 2007-08-18)
spi_controller\chart\Thumbs.db (23552, 2007-12-24)
spi_controller\chart\ͼ6-11.bmp (257598, 2007-08-18)
spi_controller\chart\ͼ6-12.bmp (499374, 2007-08-18)
spi_controller\chart\ͼ6-13.bmp (411774, 2007-08-18)
spi_controller\chart\ͼ6-14.bmp (322422, 2007-08-18)
spi_controller\chart\ͼ6-17.bmp (366222, 2007-08-18)
spi_controller\chart\ͼ6-18.bmp (411774, 2007-08-18)
spi_controller\chart\ͼ6-19.bmp (455574, 2007-08-18)
spi_controller\chart\ͼ6-7.bmp (455574, 2007-08-18)
spi_controller\spi_clgen.v (2324, 2007-08-23)
spi_controller\spi_controller.cr.mti (1967, 2007-08-23)
spi_controller\spi_controller.mpf (18973, 2007-08-23)
spi_controller\spi_defines.v (2875, 2007-08-23)
spi_controller\spi_shift.v (6758, 2007-08-23)
spi_controller\spi_slave_model.v (892, 2007-08-23)
spi_controller\spi_top.v (9868, 2007-08-23)
spi_controller\tb_spi_top.v (9355, 2007-08-23)
spi_controller\timescale.v (21, 2007-08-23)
spi_controller\transcript (648, 2007-08-23)
spi_controller\vsim.wlf (131072, 2007-08-18)
spi_controller\wave\spi_clgen.bmp (1255302, 2007-08-18)
spi_controller\wave\spi_shift.bmp (1930950, 2007-08-18)
spi_controller\wave\spi_slave_model.bmp (1126134, 2007-08-18)
spi_controller\wave\spi_top.bmp (2696022, 2007-08-18)
spi_controller\wave\tb_spi_top.bmp (1526886, 2007-08-18)
spi_controller\wave\Thumbs.db (18944, 2007-12-24)
spi_controller\wave\wb_master_model.bmp (1314918, 2007-08-18)
spi_controller\wb_master_model.v (2722, 2007-08-23)
spi_controller\work\spi_clgen\verilog.asm (11767, 2007-08-23)
spi_controller\work\spi_clgen\_primary.dat (1193, 2007-08-23)
spi_controller\work\spi_clgen\_primary.vhd (560, 2007-08-23)
spi_controller\work\spi_shift\verilog.asm (27894, 2007-08-23)
spi_controller\work\spi_shift\_primary.dat (3385, 2007-08-23)
spi_controller\work\spi_shift\_primary.vhd (1025, 2007-08-23)
spi_controller\work\spi_slave_model\verilog.asm (6627, 2007-08-23)
spi_controller\work\spi_slave_model\_primary.dat (558, 2007-08-23)
spi_controller\work\spi_slave_model\_primary.vhd (380, 2007-08-23)
spi_controller\work\spi_top\verilog.asm (32450, 2007-08-23)
spi_controller\work\spi_top\_primary.dat (4283, 2007-08-23)
... ...
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