atlys_ethernet_test_v1-20110404
所属分类:VHDL/FPGA/Verilog
开发工具:Visual C++
文件大小:3657KB
下载次数:15
上传日期:2012-04-27 18:10:25
上 传 者:
fabi
说明: this is useful for capture the raw data on Ethernet port
文件列表:
atlys_ethernet_test_v1\.DS_Store (6148, 2011-02-28)
atlys_ethernet_test_v1\_xmsgs (0, 2011-04-04)
atlys_ethernet_test_v1\_xmsgs\ngcbuild.xmsgs (367, 2011-03-30)
atlys_ethernet_test_v1\_xmsgs\pn_parser.xmsgs (815, 2011-04-04)
atlys_ethernet_test_v1\atlys_ethernet_test.gise (1473, 2011-04-04)
atlys_ethernet_test_v1\atlys_ethernet_test.xise (45957, 2011-04-01)
atlys_ethernet_test_v1\coregen (0, 2011-04-04)
atlys_ethernet_test_v1\coregen\.lso (21, 2011-02-18)
atlys_ethernet_test_v1\coregen\_xmsgs (0, 2011-03-25)
atlys_ethernet_test_v1\coregen\_xmsgs\ngcbuild.xmsgs (367, 2011-02-18)
atlys_ethernet_test_v1\coregen\_xmsgs\pn_parser.xmsgs (828, 2011-04-04)
atlys_ethernet_test_v1\coregen\_xmsgs\xst.xmsgs (61652, 2011-02-18)
atlys_ethernet_test_v1\coregen\coregen.cgc (26910, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_generator_ug175.pdf (38936, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.asy (1097, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.gise (1640, 2011-04-04)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.ncf (0, 2011-04-04)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.ngc (182907, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.sym (3001, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.v (14959, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.veo (4797, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.vhd (11713, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.vho (5471, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.xco (6253, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.xco.bak (6673, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk.xise (5140, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk_flist.txt (464, 2011-02-18)
atlys_ethernet_test_v1\coregen\fifo_xlnx_512x36_2clk_xmdf.tcl (3576, 2011-02-18)
atlys_ethernet_test_v1\coregen\tmp (0, 2011-03-25)
atlys_ethernet_test_v1\coregen\tmp\_cg (0, 2011-02-18)
atlys_ethernet_test_v1\coregen\xlnx_auto_0_xdb (0, 2011-02-18)
atlys_ethernet_test_v1\coregen_xil_3964_165.cgc (2075, 2011-02-18)
atlys_ethernet_test_v1\coregen_xil_3964_165.cgp (518, 2011-02-18)
atlys_ethernet_test_v1\debug.cdc (13029, 2011-03-30)
atlys_ethernet_test_v1\edge_detect.v (1163, 2011-04-04)
atlys_ethernet_test_v1\ethernet_test_top.cpj (63992, 2011-04-01)
atlys_ethernet_test_v1\ethernet_test_top.ucf (10522, 2011-04-01)
atlys_ethernet_test_v1\ethernet_test_top.v (11816, 2011-04-04)
atlys_ethernet_test_v1\ethernet_test_top_bitgen.xwbt (413, 2011-04-04)
... ...
Core Name: Xilinx LogiCORE FIFO Generator
Version: 7.2
Release Date: September 21, 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core,
please go to:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
For software requirements, please go to the "Software Requirements" link on that page.
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v7.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
2. NEW FEATURES
- AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only)
- ISE 12.3 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/ LXT/SXT/FXT
- Virtex-4 XC LX/SX/FX
- Virtex-4 XQ LX/SX/FX
- Virtex-4 XQR LX/SX/FX
- Spartan-3 XC
- Spartan-3 XA
- Spartan-3A XC 3A / 3A DSP / 3AN DSP
- Spartan-3A XA 3A / 3A DSP
- Spartan-3E XC
- Spartan-3E XA
4. RESOLVED ISSUES
- In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution
is set to 1600x1200 or 1900x1200.
- CR 568630
- The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected.
- CR 570314
5. KNOWN ISSUES
The following are known issues for v7.2 of this core at time of release:
- In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
- CR 467240
- AR 31379
- The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is
either Common or Independent Clock Block RAM, and the depth is ***K and the width is 36.
- CR 570041
- AR 37201
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
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Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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