详细说明：AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.

 近期下载过的用户:  陈天 运思 谢云松 w11767 刘振宇 Yongming Lee st tarik ninghuiming 李皓 张婷 [查看上载者崔崔的更多信息]

 相关搜索: 加密 verilog aes verilog代码 AES算法Verilog实现 verilog AES verilog實現 verilog aes 加密 协议 哈希 verilog 代码 AES aes_core verilog AES 源码下载 aes verilog AES协议 AES高级加密算法的verilog语言实现 encryptor.cpp 

 [rijndael(全).zip] - rijndael(全).zip，已经通过aes认证。这个源码包是全的，含有std_defs2.h文件。这儿有很多rain doll源码包都不全
 [300KindsofEncryption.rar] - 使用C实现的300中常用加密算法，例如rsa，des
 [OSSLTunnel.zip] - SSL 加密原代码 有了这个就可以对http协议get /post头进行加密
 
 [VBCrypto2.zip] - 使用VB写的加密算法库，包括Blowfish, IDEA, Triple DES (3DES), DES, DESE, Gost, Skipjack, TEA, Cast5, Serpent-128, Serpent-192, Serpent-256, Rijndael-128, Rijndael-
 [aes.rar] - aes Core Modules In this document I describe components designated to encoding and decoding using AES. aes enc — parametrizable component which can
 [aes_core.tar.gz] - aes的verilog实现,用于加密的算法硬件实现!
 [2005112916243516573.rar] - aes可执行程序，加密解密 可以进行推演
 [DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)] - 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a
 [1111111111111aes.zip] - 非常好用，实现加密解密，条用方法，很好很好，很方便
 [ 148个verilog hdl小程序（有很多testbench）——.rar] - 148个verilog hdl小程序（有很多testbench）——.
 [aes3222.zip] - aes算法源代码，是用Vicual C＋＋写的，好用

文件列表(点击判断是否您需要的文件):
  aes_core
  ........\bench
  ........\.....\CVS
  ........\.....\verilog
  ........\.....\.......\CVS
  ........\.....\.......\test_bench_top.v
  ........\CVS
  ........\doc
  ........\...\aes.pdf
  ........\...\CVS
  ........\rtl
  ........\...\CVS
  ........\...\verilog
  ........\...\.......\aes_cipher_top.v
  ........\...\.......\aes_inv_cipher_top.v
  ........\...\.......\aes_inv_sbox.v
  ........\...\.......\aes_key_expand_128.v
  ........\...\.......\aes_rcon.v
  ........\...\.......\aes_sbox.v
  ........\...\.......\CVS
  ........\...\.......\...\Entries
  ........\sim
  ........\...\CVS
  ........\...\rtl_sim
  ........\...\.......\bin
  ........\...\.......\...\CVS
  ........\...\.......\...\Makefile
  ........\...\.......\CVS
  ........\...\.......\run
  ........\...\.......\...\CVS
  ........\...\.......\...\waves
  ........\...\.......\...\.....\CVS
  ........\...\.......\...\.....\waves.do
  ........\syn
  ........\...\bin
  ........\...\...\comp.dc
  ........\...\...\CVS
  ........\...\...\design_spec.dc
  ........\...\...\lib_spec.dc
  ........\...\...\read.dc
  ........\...\CVS
  ........\vim_session.vim