sspp

所属分类:VHDL/FPGA/Verilog
开发工具:VBScript
文件大小:228KB
下载次数:31
上传日期:2006-04-18 19:02:46
上 传 者hailiang
说明:  串行输入信号经内部处理后,实现并行信号输出的功能
(serial input signal by the internal processing, parallel signal output function)

文件列表:
sp\receiver.qpf (946, 2006-01-16)
sp\receiver.qsf (2126, 2006-01-16)
sp\receiver.vhd (1892, 2006-01-16)
sp\receiver.map.eqn (9254, 2006-01-16)
sp\receiver.map.rpt (16274, 2006-01-16)
sp\receiver.flow.rpt (3813, 2006-01-16)
sp\receiver.map.summary (424, 2006-01-16)
sp\receiver.fit.eqn (11397, 2006-01-16)
sp\receiver.pin (78297, 2006-01-16)
sp\receiver.fit.rpt (147532, 2006-01-16)
sp\receiver.fit.summary (514, 2006-01-16)
sp\receiver.sof (966463, 2006-01-16)
sp\receiver.pof (1048717, 2006-01-16)
sp\receiver.asm.rpt (7410, 2006-01-16)
sp\receiver.tan.summary (1422, 2006-01-16)
sp\receiver.tan.rpt (65025, 2006-01-16)
sp\receiver.done (26, 2006-01-16)
sp\receiver.vwf (5828, 2006-01-16)
sp\receiver.sim.rpt (3851, 2006-01-16)
sp\receiver.qws (1329, 2006-01-16)
sp\cmp_state.ini (2, 2006-01-16)
sp\db\receiver.db_info (136, 2006-01-16)
sp\db\receiver_cmp.qrpt (0, 2006-01-16)
sp\db\receiver.cbx.xml (393, 2006-01-16)
sp\db\receiver.hif (438, 2006-01-16)
sp\db\receiver.(0).cnf.cdb (5599, 2006-01-16)
sp\db\receiver.(0).cnf.hdb (941, 2006-01-16)
sp\db\receiver.hier_info (523, 2006-01-16)
sp\db\receiver.rtlv_sg.cdb (4444, 2006-01-16)
sp\db\receiver.rtlv.hdb (6034, 2006-01-16)
sp\db\receiver.rtlv_sg_swap.cdb (158, 2006-01-16)
sp\db\receiver.pre_map.hdb (6041, 2006-01-16)
sp\db\receiver.pre_map.cdb (4493, 2006-01-16)
sp\db\receiver.psp (0, 2006-01-16)
sp\db\receiver.map.logdb (4, 2006-01-16)
sp\db\receiver.sgdiff.cdb (3615, 2006-01-16)
sp\db\receiver.sgdiff.hdb (7114, 2006-01-16)
sp\db\receiver.syn_hier_info (0, 2006-01-16)
sp\db\receiver.map.cdb (4025, 2006-01-16)
sp\db\receiver.map.hdb (6133, 2006-01-16)
... ...

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