EMAC6
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3518KB
下载次数:53
上传日期:2013-01-09 00:04:20
上 传 者:
trygov
说明: verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。
(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)
文件列表:
EMAC6 (0, 2012-10-30)
EMAC6\EMAC6.cgc (53160, 2012-10-30)
EMAC6\EMAC6.cgp (523, 2012-10-30)
EMAC6\tmp (0, 2012-10-30)
EMAC6\tmp\_cg (0, 2013-01-08)
EMAC6\tmp\_xmsgs (0, 2012-10-30)
EMAC6\tmp\_xmsgs\netgen.xmsgs (665, 2012-10-30)
EMAC6\tmp\_xmsgs\ngcbuild.xmsgs (367, 2012-10-30)
EMAC6\tmp\_xmsgs\pn_parser.xmsgs (766, 2012-10-30)
EMAC6\tmp\_xmsgs\xst.xmsgs (25330, 2012-10-30)
EMAC6\v6_emac_v2_1 (0, 2012-10-30)
EMAC6\v6_emac_v2_1\doc (0, 2012-10-30)
EMAC6\v6_emac_v2_1\doc\ds835_v6_emac.pdf (940112, 2012-10-30)
EMAC6\v6_emac_v2_1\doc\ug800_v6_emac.pdf (5591623, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\address_decoder.v (14969, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\axi4_lite_ipif_wrapper.v (9330, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\axi_lite_ipif.v (11991, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\counter_f.v (7032, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\pselect_f.v (6974, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_ipif\slave_attachment.v (24481, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_lite (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\axi_lite\axi_lite_sm.v (27804, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\clk_wiz.v (7216, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\common (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\common\reset_sync.v (3919, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\common\sync_block.v (3855, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\fifo (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\fifo\rx_client_fifo.v (31642, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\fifo\ten_100_1g_eth_fifo.v (7354, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\fifo\tx_client_fifo.v (56640, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen (0, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\address_swap.v (16129, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\axi_mux.v (3790, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\axi_pat_check.v (8870, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\axi_pat_gen.v (8075, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\axi_pipe.v (6408, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\pat_gen\basic_pat_gen.v (8810, 2012-10-30)
EMAC6\v6_emac_v2_1\example_design\physical (0, 2012-10-30)
... ...
Core name: Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
Version: 2.1
Release Date: March 1, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this
core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP v6_emac_v2_1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/V6_Embedded_TEMAC_Wrapper.htm
2. NEW FEATURES
- ISE 13.1 software support
- Support for AXI4-Lite
- Support for AXI4-Stream
- All new memory mapped interface
- Optional built-in statistics counters
- New example design
- 2Gbps and 2.5Gbps not suppported
3. SUPPORTED DEVICES
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-6 HXT
- Virtex-6 CXT
- Virtex-6 Lower Power
- QPro Virtex-6 Hi-Rel
4. RESOLVED ISSUES
- None
5. KNOWN ISSUES
The following are known issues for v2.1 of this core at time of release:
- 2Gbps and 2.5Gbps not suppported in this release.
- Virtex-6 Lower Power implementation just fails to meet GMII
timing specification.
- "ERROR - Testbench timed out" for some configurations during back-annotated
timing simulations when using the Synopsys VCS simulator.
- Answer Record 39960, CR 588662
- Workaround: use a different supported simulator. Alternatively, for
Synopsys VCS, remove SDF back-annotation by deleting the "-***" argument
from the vcs command.
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
This core only supports Verilog LRM-IEEE 13***-2005 encryption-compliant
simulators. See the Getting Started Guide.
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
03/2011 Xilinx, Inc. 2.1 Release for ISE 13.1
================================================================================
9. LEGAL DISCLAIMER
(c) Copyright 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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