ADSP-561-load-program
所属分类:DSP编程
开发工具:Visual C++
文件大小:4638KB
下载次数:11
上传日期:2013-01-17 11:21:38
上 传 者:
aduse
说明: ADI DSP BF561 算法相关代码
(Usage of the SCCB Software Interface for configuring I2C devices by the
Blackfin® Processor family)
文件列表:
ADSP 561 load program\ADSP-BF561\61\adi_preprocess.doj (30720, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\adi_preprocess_core.doj (3360, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\adi_ssl_Init.doj (71684, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\adi_usb_net2272.doj (176752, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\clargpar.doj (86288, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\coreA.log (8201, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\dma.doj (49888, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\encoder.doj (92648, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\encoder_config.doj (53612, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\ezkitutilities.doj (51288, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\main.doj (53644, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\ppi_ctrl.doj (4308, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\ppi_init.doj (6332, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\ppi_isr.doj (5016, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\sml2.log (1573, 2009-04-03)
ADSP 561 load program\ADSP-BF561\61\sml3.doj (7184, 2009-04-03)
ADSP 561 load program\ADSP-BF561\61\sml3.log (163, 2009-04-03)
ADSP 561 load program\ADSP-BF561\61\streamout.doj (31048, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\telem.doj (276572, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\usbio.doj (130960, 2008-12-12)
ADSP 561 load program\ADSP-BF561\61\videograbber.doj (41760, 2008-12-12)
ADSP 561 load program\ADSP-BF561\coreA.dlb (1170390, 2008-12-12)
ADSP 561 load program\ADSP-BF561\coreA.dpj (31214, 2008-09-04)
ADSP 561 load program\ADSP-BF561\coreA.mak (23634, 2008-12-12)
ADSP 561 load program\ADSP-BF561\coreA.pcf (30519, 2009-04-03)
ADSP 561 load program\ADSP-BF561\coreB.dpj (17886, 2008-09-04)
ADSP 561 load program\ADSP-BF561\coreB.pcf (2212, 2009-04-03)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561.dpg (799, 2009-04-03)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561.dpj (25513, 2008-09-04)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561.ldf (54364, 2008-09-04)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561.pcf (3701, 2009-04-03)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_AllCache_basiccrt.s (9270, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_AllCache_cplbtab561a.c (4994, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_AllCache_cplbtab561b.c (4859, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_AllCache_heaptab.c (2774, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_basiccrt.s (9042, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_cplbtab561a.c (3545, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_cplbtab561b.c (3544, 2008-06-17)
ADSP 561 load program\ADSP-BF561\mpeg4encbf561_heaptab.c (2717, 2008-06-17)
... ...
****************************************************************************************************
ADSP-BF561 EZ-KIT
Video TalkThrough Example
Analog Devices, Inc.
DSP Division
Three Technology Way
Norwood, MA 02062
Date Created: 11/11/03
Change History:
04/30/04 : eliminated silicon revision check
example now works for rev 0.2 and higher
____________________________________________________________________________________________________
This example streams input from a video source to a output screen.
A video source is aquired frame-by-frame into SDRAM from the VideoDecoder.
The frames are then output with a one-frame delay to the Encoder.
In this example, no processing is done on the frames. They are passed unaltered.
This is a dual core project. Please see section III. to get familiar with the project structure
____________________________________________________________________________________________________
Requires ADSP-BF561 silicon revision of 0.2 or higher
____________________________________________________________________________________________________
CONTENTS
I. FUNCTIONAL DESCRIPTION
II. OPERATION DESCRIPTION
III. PROJECT STRUCTURE
I. FUNCTIONAL DESCRIPTION
Core A sets up Clock frequencies, SDRAM controller, the Video Encoder and Decoder, and PPI0 to
perform the video acquisiton in ITU-656 mode. Frames are stroed in SDRAM (in a circular fashion,
4 frames at a time).
Core B sets up PPI1 to perform video output. It then waits for the first valid frame in memory
from Core A, and starts the transfers. GP output mode is used.
Both the Video Encoder and Decoder are kept in theit power on configuration, no other configuration
is done. If you need to change settings, you may do so by adding code for I2C routines.
II. OPERATION DESCRIPTION
- Open the "video_inout.dpg" project group in the VisualDSP Integrated Development
Environment (IDDE). Follow instructions in section III.
- Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP).
- Connect a video NTSC/PAL CVBS source to the bottom right connector of J6 (video in/out jack)
- Connect a video display monitor to the video output jack (top middle connector of J6)
- Dipswitch SW5: set #1 to "off", all others to on
- Dipswitch SW2: set #2,3,5 to "off", #1,4,6 to on
- Dipswitch SW3: set #1,4 to "off", #2,3 to on
- Run the executables by pressing "multiprocessor run" (CTRL-F5) on the toolbar. DO NOT use the
single core (F5) button. You should see a copy of the input video in the output screen.
- Halt the processor ("multiprocessor halt" button). If you open a memory window and go to the
addresses of _sFrame0,1,2,3, you see the video data of the four frames.
- The main header file "system.h" contains #define statements for most of the system settings
(clock frequencies etc)
III. PROJECT STRUCTURE
This is a dual core project. It consists of a main project - containing only system defines and linker settings-
".\video_inout.dpj",
four sub-projects - containing the source code -
".\coreA\coreA.dpj" ( code exclusive to core A, in L1 memory )
".\coreB\coreB.dpj" ( code exclusive to core B, in L1 memory )
".\Shared Memory L2\L2_SRAM.dpj" ( code that is shared between the cores, in on-chip L2 memory )
".\Shared Memory L3\L3_SDRAM.dpj" ( code that is shared between the cores, in off-chip L3 memory, SDRAM ),
and the project group that ties everything together:
".\video_in_out.dpg".
Follow this procedure to open and compile the project:
- open the project group (File -> Open -> Project Group)
- right click on the main project and re-build the project.
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