tse_datapath_reference_design
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5788KB
下载次数：345
上传日期：2013-01-28 22:51:16
上 传 者：
maxtek
说明： altera FPGA实现千兆以太网数据通信的程序源代码
(altera FPGA Gigabit Ethernet data communication program source code)
文件列表:
tse_datapath_reference_design\an483.pdf (1702393, 2008-02-01)
tse_datapath_reference_design\demo (0, 2008-01-18)
tse_datapath_reference_design\demo\launch_demo.sh (236, 2007-11-05)
tse_datapath_reference_design\demo\main.elf (502798, 2007-10-30)
tse_datapath_reference_design\demo\tse_ref_design_top.cdf (412, 2007-11-05)
tse_datapath_reference_design\demo\tse_ref_design_top.sof (2947978, 2008-01-18)
tse_datapath_reference_design\pof (0, 2007-11-14)
tse_datapath_reference_design\pof\altera_siigx_pcie_pfl.pof (15024, 2007-10-09)
tse_datapath_reference_design\pof\tse_ref_design_top.pof (67109095, 2008-01-18)
tse_datapath_reference_design\tse_ref_design (0, 2008-01-25)
tse_datapath_reference_design\tse_ref_design\altera_ethernet.qip (192, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet.v (17477, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet.vo (1135268, 2007-10-23)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_1.qip (194, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_1.v (17466, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_1_constraints.sdc (6013, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_1_constraints.tcl (5089, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_1_loopback.v (3328, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_constraints.sdc (5959, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_constraints.tcl (5061, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_ethernet_loopback.v (3326, 2007-10-22)
tse_datapath_reference_design\tse_ref_design\altera_tse_align_sync.v (5976, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_alt2gxb_basic.v (21784, 2007-10-16)
tse_datapath_reference_design\tse_ref_design\altera_tse_altshifttaps.v (4424, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_altsyncram_dpm_fifo.v (2920, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_a_fifo_13.v (6800, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_a_fifo_24.v (5832, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_a_fifo_34.v (5752, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_a_fifo_opt_1246.v (10568, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_bin_cnt.v (2368, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_carrier_sense.v (3288, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_clk_cntl.v (3888, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_colision_detect.v (3464, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_crc328checker.v (3848, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_crc328generator.v (2736, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_crc32ctl8.v (1888, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_crc32galois8.v (7016, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_dec10b8b.v (6344, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_dec_func.v (45024, 2007-09-27)
tse_datapath_reference_design\tse_ref_design\altera_tse_enc8b10b.v (12288, 2007-09-27)
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