[
elock.555.pdf.rar] - 单片机的电子密码锁,主要用的是电子电路的知识,要下的朋友请注意一下。
[
uP.zip] - 这是8位微处理器的
verilog源代码,可以欠在Flex10k10里面
[
YahooWatherCom.rar] - 一个实时从yahoo网站抓取天气预报的atl con组件,相信比较实用
[
I2C_IPcore_VHDL.rar] - 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核,可直接编译运行
[
iictestbench.rar] - vhdl写的完整i2c代码,有仿真文件,是清华的人写的,质量可靠,请大家交流,qq:398087764
[
i2c_slave_model_verilog.rar] - 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.
[
i2c总线.rar] - iic总线资料,非常详细的iic总线资料
[
FPGACPLD.rar] - 学习FPGA CPLD的入门文档,比较适合初学者
[
uart_v11.zip] - uart串口的vhdl语言程序。本人调试过 ,非常好用
[
1_061026140305.rar] - 基于FPGA的I2C总线模拟,采用
verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.
文件列表(日期:2001092420~2009021210)(点击判断是否您需要的文件,如果是垃圾请在下面评价投诉):
i2c
...\bench
...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\
i2c_slave_model.v ...\.....\.......\i2c_slave_model.v.bak
...\.....\.......\
spi_slave_model.v ...\.....\.......\spi_slave_model.v.bak
...\.....\.......\
tst_bench_top.v ...\.....\.......\tst_bench_top.v.bak
...\.....\.......\
wb_master_model.v ...\.....\.......\wb_master_model.v.bak
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\doc
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_specs.pdf
...\...\src
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\I2C_specs.doc
...\rtl
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\
i2c_master_bit_ctrl.v ...\...\.......\i2c_master_bit_ctrl.v.bak
...\...\.......\
i2c_master_byte_ctrl.v ...\...\.......\i2c_master_byte_ctrl.v.bak
...\...\.......\
i2c_master_defines.v ...\...\.......\
i2c_master_top.v ...\...\.......\i2c_master_top.v.bak
...\...\.......\timescale.v
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\
I2C.VHD ...\...\....\
i2c_master_bit_ctrl.vhd ...\...\....\
i2c_master_byte_ctrl.vhd ...\...\....\
i2c_master_top.vhd ...\...\....\
readme ...\...\....\
tst_ds1621.vhd ...\sim
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c.cr.mti
...\...\i2c.mpf
...\...\i2c_verilog
...\...\...........\CVS
...\...\...........\...\Entries
...\...\...........\...\Repository
...\...\...........\...\Root
...\...\...........\run
...\...\...........\...\bench.vcd
...\...\...........\...\CVS
...\...\...........\...\...\Entries
...\...\...........\...\...\Repository
...\...\...........\...\...\Root
...\...\...........\...\INCA_libs
...\...\...........\...\.........\CVS
...\...\...........\...\.........\...\Entries
...\...\...........\...\.........\...\Repository
...\...\...........\...\.........\...\Root
...\...\...........\...\ncverilog.key
...\...\...........\...\ncverilog.log
...\...\...........\...\
run ...\...\...........\...\waves
...\...\...........\...\.....\CVS
...\...\...........\...\.....\...\Entries
...\...\...........\...\.....\...\Repository
...\...\...........\...\.....\...\Root
...\...\vsim.wlf
...\...\work
...\...\....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e
...\...\....\............................\verilog.asm
...\...\....\............................\_primary.dat