pci_core_verilog
所属分类：超算/并行计算
开发工具：Others
文件大小：211KB
下载次数：355
上传日期：2007-11-12 22:40:53
上 传 者：
bbwind
说明： PCI-master的核，verilog语言，经测试，可完成芯片的综合及布线
(PCI-master s nuclear, verilog language, by testing, to be completed by the integrated chip and wiring)
文件列表:
rtl\' (18424, 2007-05-19)
rtl\bus_commands.v (26088, 2007-05-18)
rtl\pci_async_reset_flop(1).v (26354, 2007-05-18)
rtl\pci_async_reset_flop.v (25018, 2007-05-18)
rtl\pci_bridge32(1).v (95282, 2007-05-18)
rtl\pci_bridge32.v (44614, 2007-05-18)
rtl\pci_cbe_en_crit(1).v (25629, 2007-05-18)
rtl\pci_cbe_en_crit.v (24883, 2007-05-18)
rtl\pci_conf_cyc_addr_dec(1).v (27198, 2007-05-18)
rtl\pci_conf_cyc_addr_dec.v (25045, 2007-05-18)
rtl\pci_conf_space(1).v (173686, 2007-05-18)
rtl\pci_conf_space.v (33880, 2007-05-18)
rtl\pci_constants(1).v (29567, 2007-05-18)
rtl\pci_constants.v (26454, 2007-05-18)
rtl\pci_cur_out_reg(1).v (30116, 2007-05-18)
rtl\pci_cur_out_reg.v (24883, 2007-05-18)
rtl\pci_delayed_sync(1).v (40488, 2007-05-18)
rtl\pci_delayed_sync.v (26999, 2007-05-18)
rtl\pci_delayed_write_reg(1).v (25848, 2007-05-18)
rtl\pci_delayed_write_reg.v (25045, 2007-05-18)
rtl\pci_frame_crit(1).v (24856, 2007-05-18)
rtl\pci_frame_crit.v (25547, 2007-05-18)
rtl\pci_frame_en_crit.v (24937, 2007-05-18)
rtl\pci_wbr_fifo_control(1).v (28232, 2007-05-19)
rtl\pci_wbr_fifo_control.v (31575, 2007-05-19)
rtl\pci_wbs_wbb3_2_wbb2(1).v (28416, 2007-05-19)
rtl\pci_wbs_wbb3_2_wbb2.v (30427, 2007-05-19)
rtl\pci_wbw_fifo_control(1).v (32696, 2007-05-19)
rtl\pci_wbw_fifo_control.v (29330, 2007-05-19)
rtl\pci_wbw_wbr_fifos(1).v (31175, 2007-05-19)
rtl\pci_wbw_wbr_fifos.v (46521, 2007-05-19)
rtl\pci_wb_tpram.v (33555, 2007-05-19)
rtl\timescale(1).v (22418, 2007-05-19)
rtl\timescale.v (26511, 2007-05-19)
rtl (0, 2007-05-21)
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