说明：  本设计的基本要求是以复杂可编程逻辑器件CPLD为基础，通过在EDA系统软件ispDesignExpert System 环境下进行数字系统设计，熟练掌握该环境下的功能仿真，时间仿真，管脚锁定和芯片下载。 本系统基本上比较全面的模拟了计数式数字频率计，广泛应用于工业、民用等各个领域，具有一定的开发价值。
( This design basic request is take complex programmable logical component CPLD as a foundation, through environment carries on the number system design in EDA system software ispDesignExpert under the System, skilled grasps under this environment the function simulation, the time simulation, base pin locking and chip downloading. This system basically quite comprehensive simulation has counted the numerical expression numeral frequency meter, widely applies to the industry, civilly and so on each domain, has the certain development value. )