vertex5_digilent_emac0_1gbps
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:6882KB
下载次数:13
上传日期:2013-07-20 10:01:44
上 传 者:
rickhjl
说明: Digilent公司开发板GENESYS板载1Gbps网口实现驱动程序,实现回环模式的发送。
(Digilent development board GENESYS onboard 1Gbps ethernet driver, send the loopback mode)
文件列表:
final_emac_with_macaddress\1.cpj (18243, 2013-07-17)
final_emac_with_macaddress\configuration_tb_isim_beh.exe (82432, 2013-07-15)
final_emac_with_macaddress\dcm.tfi (242, 2013-07-15)
final_emac_with_macaddress\dcm.v (3357, 2013-07-15)
final_emac_with_macaddress\dcm_arwz.ucf (883, 2013-07-15)
final_emac_with_macaddress\emac_scope.cdc (4536, 2013-07-16)
final_emac_with_macaddress\final_emac_with_macaddress.gise (26208, 2013-07-17)
final_emac_with_macaddress\final_emac_with_macaddress.xise (41430, 2013-07-17)
final_emac_with_macaddress\frame_typ_e0_isim_beh.exe (82432, 2013-07-15)
final_emac_with_macaddress\frame_typ_e0_stx_beh.prj (132, 2013-07-15)
final_emac_with_macaddress\fuse.log (7769, 2013-07-17)
final_emac_with_macaddress\fuse.xmsgs (367, 2013-07-17)
final_emac_with_macaddress\fuseRelaunch.cmd (318, 2013-07-17)
final_emac_with_macaddress\hwcosim_compile.log (26995, 2013-07-15)
final_emac_with_macaddress\hwcosim_xst.prj (1307, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\coregen.cgp (238, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\coregen.log (1169, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\create_dcm.tcl (1248, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\create_v5emac.tcl (1329, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\dcm.v (3424, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\dcm.xaw (3602, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\dcm_arwz.ucf (883, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\dcm_flist.txt (49, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\tmp\_xmsgs\pn_parser.xmsgs (837, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\doc\v5_emac_ds550.pdf (338996, 2011-02-04)
final_emac_with_macaddress\ipcore_dir\v5emac\doc\v5_emac_gsg340.pdf (2430241, 2011-02-04)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\address_swap_module_8.v (15030, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\address_swap_module_8.vhd (14530, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\eth_fifo_8.v (8409, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\eth_fifo_8.vhd (10123, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\rx_client_fifo_8.v (30880, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\rx_client_fifo_8.vhd (35216, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\tx_client_fifo_8.v (45003, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\client\fifo\tx_client_fifo_8.vhd (53005, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\physical\gmii_if.v (9083, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\physical\gmii_if.vhd (8866, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\v5emac.v (23551, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\v5emac.vhd (24126, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\v5emac_block.v (13872, 2013-07-15)
final_emac_with_macaddress\ipcore_dir\v5emac\example_design\v5emac_block.vhd (18558, 2013-07-15)
... ...
Core name: Xilinx LogiCORE Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
Version: 1.8
Release Date: March 01, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP v5_emac_v1_8
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/V5_Embedded_TEMAC_Wrapper.htm
2. NEW FEATURES
- ISE 13.1 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Virtex-5 XC LXT/SXT/TXT/FXT
Virtex-5 XQ LXT/SXT/FXT
4. RESOLVED ISSUES
- N/A
5. KNOWN ISSUES
The following are known issues for v1.8 of this core at time of release:
- When EMAC0 and EMAC1 are both enabled and configured for tri-speed
operation, the GMII physical interface, and standard clocking, Map fails
with the following error:
"ERROR:Place:592 - A clock IOB / BUFGCTRL clock component pair have been
found that are not placed at an optimal clock IOB / BUFGCTRL site pair."
- CR 539043
Please see this core's Answer Record for solutions to this issue
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
This core only supports Verilog LRM-IEEE 13***-2005 encryption-compliant
simulators. See the Getting Started Guide.
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
03/01/2011 Xilinx, Inc. 1.8 ISE 13.1 support
04/19/2010 Xilinx, Inc. 1.7 ISE 12.1 support
04/24/2009 Xilinx, Inc. 1.6 ISE 11.1 support
09/19/2008 Xilinx, Inc. 1.5 Virtex-5 TXT support
03/24/2008 Xilinx, Inc. 1.4 ISE 10.1 support
08/08/2007 Xilinx, Inc. 1.3 ISE 9.2i support
02/15/2007 Xilinx, Inc. 1.2 ISE 9.1i support
10/23/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
9. LEGAL DISCLAIMER
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, ... ...
近期下载者:
相关文件:
收藏者: