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.gitignore (670, 2017-04-26) (1804, 2017-04-26)
Makefile (1125, 2017-04-26)
crc.vhd (2151, 2017-04-26)
crc32.vhd (1732, 2017-04-26)
crc32_tb.vhd (5049, 2017-04-26)
ethernet.vhd (9449, 2017-04-26)
ethernet_mac.xise (45025, 2017-04-26)
ethernet_mac_tb.vhd (30100, 2017-04-26)
ethernet_types.vhd (1184, 2017-04-26)
ethernet_with_fifos.vhd (7061, 2017-04-26)
framing.vhd (13660, 2017-04-26)
framing_common.vhd (2022, 2017-04-26)
generic (0, 2017-04-26)
generic\single_signal_synchronizer_simple.vhd (608, 2017-04-26)
mii_gmii.vhd (6129, 2017-04-26)
mii_gmii_io.vhd (1304, 2017-04-26)
miim.vhd (6154, 2017-04-26)
miim_control.vhd (9027, 2017-04-26)
miim_registers.vhd (9676, 2017-04-26)
miim_types.vhd (776, 2017-04-26)
reset_generator.vhd (1697, 2017-04-26)
rx_fifo.vhd (14045, 2017-04-26)
single_signal_synchronizer.vhd (654, 2017-04-26)
test (0, 2017-04-26)
test\test_common.vhd (1416, 2017-04-26)
test\test_instance.vhd (5263, 2017-04-26)
tx_fifo_adapter.vhd (4834, 2017-04-26)
utility.vhd (2361, 2017-04-26)
xilinx (0, 2017-04-26)
xilinx\fixed_input_delay.vhd (2594, 2017-04-26)
xilinx\input_buffer.vhd (1844, 2017-04-26)
xilinx\ipcore_dir (0, 2017-04-26)
xilinx\ipcore_dir\ethernet_mac_tx_fifo_xilinx.xco (7124, 2017-04-26)
xilinx\ipcore_dir\ethernet_mac_tx_fifo_xilinx.xise (5048, 2017-04-26)
xilinx\mii_gmii_io_spartan6.vhd (6802, 2017-04-26)
xilinx\output_buffer.vhd (1171, 2017-04-26)
xilinx\single_signal_synchronizer_spartan6.vhd (1812, 2017-04-26)
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# 10/100/1000 VHDL Ethernet MAC This tri-mode full-duplex Ethernet MAC sublayer was developed in VHDL as an alternative to both commercial and free implementations for usage on FPGAs. Its main distinction is the focus on simplicity both in the external user interface and internal operation. Only essential Ethernet functionality is supported. The core fully works on Xilinx Spartan 6 family FPGAs only at the moment. It was verified on hardware on a Trenz Electronic GmbH TE0600 GigaBee micromodule with a TE0603 baseboard. The user interface is comprised of two FIFOs with a 8-bit data bus for packet transmission and reception, respectively. This page is a short overview of the features and usage of the MAC. More information on the design and implementation can be found in the design document at Features ------- Finished: - **Full-duplex IEEE 802.3 communication** on copper at 10 (10BASE-T), 100 (100BASE-TX), and 1000 (1000BASE-T) Mb/s physical link speed - Achievable **data rate very close to theoretical maximum** - Generation of Ethernet preamble and frame check sequence on transmission - Verification of received packets (preamble, size, frame check sequence) - Filtering received packets by destination MAC address - MAC address insertion into source address of outgoing packets (only when the first source address byte in the packet stream is `0xFF`) - **Simple 8 bit wide FIFO user interface** with arbitrary clock domains for packet transmission and reception - **Media-independent interface (MII)** for 10/100 Mb/s and **gigabit media-independent interface (GMII)** connectivity - MII/GMII hardware I/O setup for Xilinx Spartan 6 family FPGAs - Basic **media-independent interface management (MIIM) interface support** that: - Configures the PHY auto-negotiation to use full-duplex modes only - Polls the current PHY link state and speed by reading the status and auto-negotiation registers Decisively not supported: - CSMA/CD (which effectively means **no half-duplex connections**) - Flow control with PAUSE frames - Energy-efficient Ethernet - Multicast reception filter - On-chip buses (can be integrated with custom code if needed) - Runtime configuration of core features and parameters - Manual link speed configuration via MIIM - Packet counters/statistics Ideas for the future: - Replacement of the TX FIFO that is currently generated by the Xilinx core generator with a custom VHDL implementation - Reduced gigabit media-independent interface (RGMII) support Preparation ------- Using the core currently requires an installation of Xilinx ISE 14.7 (WebPack will work) for the TX FIFO generation. In preparation for both running the testbench and using the MAC in a project, please follow these steps: - Open the project file `ethernet_mac.xise` in the ISE project navigator - Select the root node "xc6slx45-2fgg484" in the hierarchy view - Run the "Regenerate All Cores" process under "Design Utilities" Verifying the design ------- The source code includes the self-checking testbench entity `ethernet_mac_tb`. If you have [GHDL]( and make installed, you can start a basic functional verification in a behavioral simulation of the core by simply running $ make prepare ISE_DIR=/path/to/14.7/ISE_DS/ISE $ make check If everything works as expected, the last output line should read `MAC functional check ended OK`. Note that by default only a reduced set of tests is performed, you can modify the `TEST_THOROUGH` generic in `ethernet_mac_tb.vhd` to run the full test suite. ModelSim also works fine when you have the Xilinx libraries correctly imported. ISim will not unfortunately as it needs excessive amounts of system RAM when running the testbench. Post-synthesis verification is also supported with the XC6SLX45-2FGG484 FPGA as sample target device. To get ... ...