93C46.rar

  • hwdz
    了解作者
  • Visual Basic
    开发工具
  • 210KB
    文件大小
  • rar
    文件格式
  • 0
    收藏次数
  • 1 积分
    下载积分
  • 33
    下载次数
  • 2009-12-14 15:01
    上传日期
使用PC机并口作上位机操作93C46,需要inpout32.dll支持。
93C46.rar
  • 器件说明.txt
    847B
  • 93C46.pdf
    250KB
  • Form1.frm
    15.9KB
  • 工程1.vbp
    691B
  • 操作心得.txt
    1.1KB
  • Form1.frx
    1.4KB
  • Module1.bas
    247B
  • 工程1.vbw
    79B
  • 93C46.exe
    40KB
内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/622baf6e15da9b288b84b4b1/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622baf6e15da9b288b84b4b1/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"><span class="fc2 sc0">1</span></div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">1</div><div class="t m1 x2 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0">2</div><div class="t m1 x2 h3 y4 ff2 fs1 fc0 sc0 ls0 ws0">3</div><div class="t m1 x2 h3 y5 ff2 fs1 fc0 sc0 ls0 ws0">4</div><div class="t m1 x3 h3 y6 ff2 fs1 fc0 sc0 ls0 ws0">8</div><div class="t m1 x3 h3 y7 ff2 fs1 fc0 sc0 ls0 ws0">7</div><div class="t m1 x3 h3 y8 ff2 fs1 fc0 sc0 ls0 ws0">6</div><div class="t m1 x3 h3 y9 ff2 fs1 fc0 sc0 ls0 ws0">5</div><div class="t m1 x4 h3 ya ff2 fs1 fc0 sc0 ls0 ws0">CS</div><div class="t m1 x4 h3 yb ff2 fs1 fc0 sc0 ls0 ws0">SK</div><div class="t m1 x5 h3 yc ff2 fs1 fc0 sc0 ls0 ws0">DI</div><div class="t m1 x6 h3 yd ff2 fs1 fc0 sc0 ls0 ws0">DO</div><div class="t m1 x7 h3 ye ff2 fs1 fc0 sc0 ls0 ws0">VCC</div><div class="t m1 x7 h3 yf ff2 fs1 fc0 sc0 ls0 ws0">DC</div><div class="t m1 x7 h3 y10 ff2 fs1 fc0 sc0 ls0 ws0">ORG</div><div class="t m1 x7 h3 y11 ff2 fs1 fc0 sc0 ls0 ws0">GND</div><div class="t m1 x8 h3 y12 ff2 fs1 fc0 sc0 ls0 ws0">1</div><div class="t m1 x8 h3 y13 ff2 fs1 fc0 sc0 ls0 ws0">2</div><div class="t m1 x8 h3 y14 ff2 fs1 fc0 sc0 ls0 ws0">3</div><div class="t m1 x8 h3 y15 ff2 fs1 fc0 sc0 ls0 ws0">4</div><div class="t m1 x9 h3 y16 ff2 fs1 fc0 sc0 ls0 ws0">8</div><div class="t m1 x9 h3 y17 ff2 fs1 fc0 sc0 ls0 ws0">7</div><div class="t m1 x9 h3 y18 ff2 fs1 fc0 sc0 ls0 ws0">6</div><div class="t m1 x9 h3 y19 ff2 fs1 fc0 sc0 ls0 ws0">5</div><div class="t m1 xa h3 y1a ff2 fs1 fc0 sc0 ls0 ws0">CS</div><div class="t m1 xa h3 y1b ff2 fs1 fc0 sc0 ls0 ws0">SK</div><div class="t m1 xb h3 y1c ff2 fs1 fc0 sc0 ls0 ws0">DI</div><div class="t m1 xc h3 y1d ff2 fs1 fc0 sc0 ls0 ws0">DO</div><div class="t m1 xd h3 y16 ff2 fs1 fc0 sc0 ls0 ws0">VCC</div><div class="t m1 xd h3 y17 ff2 fs1 fc0 sc0 ls0 ws0">DC</div><div class="t m1 xd h3 y18 ff2 fs1 fc0 sc0 ls0 ws0">ORG</div><div class="t m1 xd h3 y19 ff2 fs1 fc0 sc0 ls0 ws0">GND</div><div class="t m1 xe h3 y1e ff2 fs1 fc0 sc0 ls0 ws0">1</div><div class="t m1 xe h3 y1f ff2 fs1 fc0 sc0 ls0 ws0">2</div><div class="t m1 xe h3 y20 ff2 fs1 fc0 sc0 ls0 ws0">3</div><div class="t m1 xe h3 y21 ff2 fs1 fc0 sc0 ls0 ws0">4</div><div class="t m1 xf h3 y22 ff2 fs1 fc0 sc0 ls0 ws0">8</div><div class="t m1 xf h3 y23 ff2 fs1 fc0 sc0 ls0 ws0">7</div><div class="t m1 xf h3 y24 ff2 fs1 fc0 sc0 ls0 ws0">6</div><div class="t m1 xf h3 y25 ff2 fs1 fc0 sc0 ls0 ws0">5</div><div class="t m1 x10 h3 y1e ff2 fs1 fc0 sc0 ls0 ws0">CS</div><div class="t m1 x10 h3 y1f ff2 fs1 fc0 sc0 ls0 ws0">SK</div><div class="t m1 x11 h3 y20 ff2 fs1 fc0 sc0 ls0 ws0">DI</div><div class="t m1 xb h3 y21 ff2 fs1 fc0 sc0 ls0 ws0">DO</div><div class="t m1 x12 h3 y1e ff2 fs1 fc0 sc0 ls0 ws0">VCC</div><div class="t m1 x12 h3 y1f ff2 fs1 fc0 sc0 ls0 ws0">DC</div><div class="t m1 x12 h3 y20 ff2 fs1 fc0 sc0 ls0 ws0">ORG</div><div class="t m1 x12 h3 y21 ff2 fs1 fc0 sc0 ls0 ws0">GND</div><div class="t m1 x2 h4 y26 ff3 fs2 fc1 sc0 ls0 ws0">8-lead PDIP</div><div class="t m1 x2 h4 y27 ff3 fs2 fc1 sc0 ls0 ws0">8-lead SOIC</div><div class="t m1 xe h4 y28 ff3 fs2 fc1 sc0 ls0 ws0">8-lead TSSOP</div><div class="t m2 x13 h5 y29 ff1 fs3 fc0 sc0 ls1 ws0">Features</div><div class="t m2 x13 h2 y2a ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 ls2 ws1">Medium-voltage and Standard-voltage Operation</span></div><div class="t m2 x14 h6 y2b ff1 fs4 fc0 sc0 ls3 ws2">&#8211;<span class="_ _1"> </span>2.7 (V</div><div class="t m2 x15 h7 y2c ff1 fs5 fc0 sc0 ls4 ws0">CC</div><div class="t m2 x16 h6 y2b ff1 fs4 fc0 sc0 ls5 ws3"> = 2.7V to 5.5V)</div><div class="t m2 x13 h2 y2d ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 ls6 ws4">User-selectable Internal Or<span class="_ _2"></span>ganization</span></div><div class="t m2 x14 h6 y2e ff1 fs4 fc0 sc0 ls7 ws5">&#8211;<span class="_ _1"> </span>1K: 128 x 8 or 64 x 16</div><div class="t m2 x13 h2 y2f ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 ls8 ws6">Three-wire Serial Interface</span></div><div class="t m2 x13 h2 y30 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 ls9 ws7">2 MHz Clock Rate (5V)</span></div><div class="t m2 x13 h2 y31 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 lsa ws8">Self-timed Write Cyc<span class="_ _2"></span>le (10 ms max)</span></div><div class="t m2 x13 h2 y32 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 lsb ws9">High Reliability</span></div><div class="t m2 x14 h6 y33 ff1 fs4 fc0 sc0 lsc wsa">&#8211;<span class="_ _1"> </span>Enduran<span class="_ _2"></span>ce: 1 Million Writ<span class="_ _2"></span>e Cyc<span class="_ _2"></span>les</div><div class="t m2 x14 h6 y34 ff1 fs4 fc0 sc0 ls6 ws4">&#8211;<span class="_ _1"> </span>Data Retention: 100 Y<span class="_ _3"></span>ears</div><div class="t m2 x13 h2 y35 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs4 ls8 ws6">8-lead PDIP<span class="_ _4"></span>, 8-lead TSSOP an<span class="lsd wsb">d 8-lead JEDEC SOIC P<span class="_ _2"></span>acka<span class="_ _2"></span>ges</span></span></div><div class="t m2 x13 h5 y36 ff1 fs3 fc0 sc0 lse ws0">Description</div><div class="t m2 x13 h2 y37 ff2 fs0 fc0 sc0 lsf wsc">The A<span class="_ _4"></span>T9<span class="ff4 ls0 ws0">3</span><span class="ls10 wsd">C46 provides 1024 bits of serial electr<span class="_ _5"></span>ically erasable prog<span class="_ _2"></span>rammable read</span></div><div class="t m2 x13 h2 y38 ff2 fs0 fc0 sc0 ls11 wse">only memory (EEPROM) orga<span class="_ _2"></span>nized a<span class="_ _2"></span>s 64 w<span class="_ _2"></span>ords of 16 bits <span class="_ _2"></span>each, when the<span class="_ _2"></span> ORG pin is</div><div class="t m2 x13 h2 y39 ff2 fs0 fc0 sc0 ls12 wsf">connected to VCC and 12<span class="_ _2"></span><span class="ff4 ls0 ws0">8<span class="ff2 ls13 ws10"> words o<span class="_ _5"></span>f </span>8<span class="ff2 ls14 ws10"> bits each <span class="_ _2"></span>when it is tied t<span class="_ _2"></span>o ground.<span class="_ _2"></span> The de<span class="_ _2"></span>vice</span></span></div><div class="t m2 x13 h2 y3a ff2 fs0 fc0 sc0 ls15 ws11">is optimized f<span class="_ _3"></span>or use in many automotiv<span class="_ _2"></span>e applications where lo<span class="_ _2"></span>w pow<span class="_ _2"></span>er and low v<span class="_ _3"></span>oltage</div><div class="t m2 x13 h2 y3b ff2 fs0 fc0 sc0 ls16 ws12">operation<span class="_ _2"></span>s are essential. Th<span class="_ _2"></span>e A<span class="_ _4"></span>T<span class="_ _2"></span>9<span class="ff4 ls0 ws0">3</span><span class="ls17 ws13">C46 is av<span class="_ _2"></span>ailabl<span class="_ _2"></span>e in space-saving <span class="ff4 ls0 ws0">8</span><span class="ls18 ws14">-lead PDIP<span class="_ _6"></span>, <span class="ff4 ls0 ws0">8<span class="ff2">-</span></span></span></span></div><div class="t m2 x13 h2 y3c ff2 fs0 fc0 sc0 ls19 ws15">lead T<span class="ff4 ls1a ws0">SS</span><span class="ls1b ws16">OP and <span class="ff4 ls0 ws0">8</span><span class="ls1c ws17">-lead JEDEC <span class="ff4 ls0 ws0">S</span><span class="ls10 ws18">OIC packages. The A<span class="_ _7"></span>T9<span class="ff4 ls0 ws0">3</span><span class="ls1d ws19">C46 is enabled through</span></span></span></span></div><div class="t m2 x13 h2 y3d ff2 fs0 fc0 sc0 ls1e ws1a">the Chip <span class="ff4 ls0 ws0">S</span><span class="ls1f ws1b">elect pin (C<span class="ff4 ls0 ws0">S</span><span class="ls20 ws1c">), and accessed via a <span class="ff4 ls0 ws0">3</span><span class="ls21 ws1d">-wire serial interf<span class="_ _2"></span>ac<span class="ls22 ws1e">e consist<span class="_ _5"></span>ing of Data</span></span></span></span></div><div class="t m2 x13 h2 y3e ff2 fs0 fc0 sc0 ls23 ws1f">Input (DI), D<span class="_ _5"></span>ata Output (DO),<span class="_ _5"></span> and <span class="ff4 ls0 ws0">S</span><span class="ls24 ws20">hift Clock (<span class="ff4 ls0 ws0">S</span><span class="ls25 ws21">K). Upon receiving a Read instr<span class="_ _5"></span>uction</span></span></div><div class="t m2 x13 h2 y3f ff2 fs0 fc0 sc0 ls26 ws22">at DI, the add<span class="_ _2"></span>ress is decoded a<span class="_ _2"></span>nd the data is cloc<span class="_ _2"></span>k<span class="_ _2"></span>ed out<span class="_ _2"></span> serially on the data<span class="_ _2"></span> output</div><div class="t m2 x13 h2 y40 ff2 fs0 fc0 sc0 ls27 ws23">pin DO<span class="_ _2"></span>. The WRITE cycle is completely<span class="_ _2"></span><span class="ls28 ws24"> self-timed and no separate erase cycle is</span></div><div class="t m2 x13 h2 y41 ff2 fs0 fc0 sc0 ls10 ws18">required before write<span class="_ _2"></span>. The Write cycle is onl<span class="ls29 ws25">y enabled when it is in the Er<span class="_ _2"></span>ase/Write</span></div><div class="t m2 x13 h2 y42 ff2 fs0 fc0 sc0 ls2a ws26">Enable state. When C<span class="ff4 ls0 ws0">S</span><span class="ls2b ws27"> is brought &#8220;high&#8221; f<span class="_ _2"></span>ollowing <span class="_ _2"></span>the initiation of a write cycle, the DO</span></div><div class="t m2 x13 h2 y43 ff2 fs0 fc0 sc0 ls2c ws0">pin outputs<span class="_ _5"></span> the Ready/Busy s<span class="_ _5"></span>tatus.</div><div class="t m2 x13 h2 y44 ff2 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m2 x13 h2 y45 ff1 fs0 fc0 sc0 ls2d ws28">T<span class="_ _4"></span>able 1. <span class="ff2 ls2e ws29">Pin Configuration</span></div><div class="t m2 x17 h6 y46 ff1 fs4 fc0 sc0 ls2f ws2a">Pin Name<span class="_ _8"> </span>Function</div><div class="t m2 x17 h6 y47 ff2 fs4 fc0 sc0 ls0 ws0">C<span class="ff4">S<span class="_ _9"> </span></span><span class="ls7">Chip </span><span class="ff4">S</span><span class="ls30">elect</span></div><div class="t m2 x17 h6 y48 ff4 fs4 fc0 sc0 ls0 ws0">S<span class="ff2">K<span class="_ _a"> </span></span>S<span class="ff2 ls31 ws2b">erial Data Clock</span></div><div class="t m2 x17 h6 y49 ff2 fs4 fc0 sc0 ls32 ws0">DI<span class="_ _b"> </span><span class="ff4 ls0">S</span><span class="ls33 ws2c">erial Data Input</span></div><div class="t m2 x17 h6 y4a ff2 fs4 fc0 sc0 ls32 ws0">DO<span class="_ _c"> </span><span class="ff4 ls0">S</span><span class="ls31 ws2b">erial Data Output</span></div><div class="t m2 x17 h6 y4b ff2 fs4 fc0 sc0 ls34 ws0">GND<span class="_ _d"> </span>Ground</div><div class="t m2 x17 h6 y4c ff2 fs4 fc0 sc0 ls35 ws0">VCC<span class="_ _e"> </span>P<span class="_ _2"></span>o<span class="_ _2"></span>wer <span class="ff4 ls0">S</span><span class="ls3">upply</span></div><div class="t m2 x17 h6 y4d ff2 fs4 fc0 sc0 ls36 ws2d">ORG<span class="_ _f"> </span>Internal Organ<span class="_ _2"></span>ization</div><div class="t m2 x18 h8 y4e ff1 fs6 fc0 sc0 ls0 ws0">Three-wire </div><div class="t m2 x18 h8 y4f ff1 fs6 fc0 sc0 ls37 ws0">Serial</div><div class="t m2 x18 h8 y50 ff1 fs6 fc0 sc0 ls0 ws0">Automotive</div><div class="t m2 x18 h8 y51 ff1 fs6 fc0 sc0 ls38 ws0">EEPROMs</div><div class="t m2 x18 h9 y52 ff1 fs7 fc0 sc0 ls39 ws2e">1K (128 x 8 or 64 x 16)</div><div class="t m2 x18 h8 y53 ff1 fs6 fc0 sc0 ls3a ws0">AT<span class="_ _10"></span>9<span class="_ _10"></span>3<span class="_ _10"></span>C<span class="_ _10"></span>4<span class="_ _10"></span>6</div><div class="t m2 x19 ha y54 ff2 fs8 fc0 sc0 ls3b ws2f">Rev. 5125A&#8211;<span class="ff4 ls0 ws0">S<span class="ff2 ls3c">EEPR&#8211;<span class="_ _2"></span><span class="ff4 ls0">8<span class="ff2 ls3d">/05</span></span></span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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