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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _0"> </span> </div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y4 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y5 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y6 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y7 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h3 y8 ff2 fs1 fc0 sc0 ls1 ws1">PCI Expr<span class="_ _1"></span>ess</div><div class="t m0 x4 h4 y9 ff2 fs2 fc0 sc0 ls0 ws0">™</div><div class="t m0 x5 h3 ya ff2 fs1 fc0 sc0 ls2 ws0"> </div><div class="t m0 x6 h3 yb ff2 fs1 fc0 sc0 ls3 ws2">Base Specifica<span class="_ _2"></span>tion </div><div class="t m0 x7 h3 yc ff2 fs1 fc0 sc0 ls1 ws3">R<span class="_ _2"></span>e<span class="_ _3"></span>vision 1.1 </div><div class="t m0 x8 h5 yd ff1 fs2 fc0 sc0 ls4 ws4">March 28, 2005 </div><div class="t m0 x9 h6 ye ff1 fs3 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h6 yf ff1 fs3 fc1 sc0 ls0 ws0"> </div><div class="t m0 xa h7 y10 ff1 fs4 fc1 sc0 ls0 ws0"> </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/bg2.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _4"></span><span class="ls5">2 </span></div><div class="t m0 xb h8 y11 ff3 fs3 fc1 sc0 ls6 ws5">Revision Rev<span class="_ _2"></span>ision <span class="_ _5"></span>History <span class="_ _6"> </span>DATE </div><div class="t m0 xb h6 y12 ff1 fs3 fc1 sc0 ls7 ws6">1.0 Initial <span class="_ _7"></span>release. <span class="_ _8"> </span>07/22/02 </div><div class="t m0 xb h6 y13 ff1 fs3 fc1 sc0 ls0 ws7">1.0a <span class="_ _9"> </span>Incorporated Errata C1-C66 and E1-E4.17. <span class="_ _a"> </span>04/15/03 </div><div class="t m0 xb h6 y14 ff1 fs3 fc1 sc0 ls8 ws8">1.1 <span class="_ _b"> </span>Incorporated approved Errata and ECNs. <span class="_ _c"> </span>03/28/05 </div><div class="t m0 x9 h9 y15 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y16 ff4 fs5 fc1 sc0 ls0 ws0">PCI-SIG disclaims all warranties and liability for the use of this document and the information </div><div class="t m0 x9 h9 y17 ff4 fs5 fc1 sc0 ls9 ws9">contained herein and assumes no responsibility for any <span class="lsa wsa">errors that may appear in this document, nor </span></div><div class="t m0 x9 h9 y18 ff4 fs5 fc1 sc0 lsb wsb">does PCI-SIG make a commitment to update the information contained her<span class="_ _1"></span>ein. </div><div class="t m0 x9 h9 y19 ff4 fs5 fc1 sc0 lsc wsc">Contact the PCI-SIG office to obtain the la<span class="wsd">test revision of this specification. </span></div><div class="t m0 x9 h9 y1a ff4 fs5 fc1 sc0 lsa wse">Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be </div><div class="t m0 x9 h9 y1b ff4 fs5 fc1 sc0 lsd wsf">forwarded to: </div><div class="t m0 xc h9 y1c ff5 fs5 fc1 sc0 lse ws10">Membership Services<span class="ff4 ls0 ws0"> </span></div><div class="t m0 xc h9 y1d ff4 fs5 fc1 sc0 ls9 ws0">www.pcisig.com </div><div class="t m0 xc h9 y1e ff4 fs5 fc1 sc0 ls0 ws11">E-mail: <span class="_ _d"> </span>administration@pcisig.com </div><div class="t m0 xc h9 y1f ff4 fs5 fc1 sc0 lse ws12">Phone: <span class="_ _e"> </span>503-291-2569 </div><div class="t m0 xc h9 y20 ff4 fs5 fc1 sc0 lsf ws13">Fax: <span class="_ _f"> </span>503-297-1090 </div><div class="t m0 xc ha y21 ff4 fs4 fc1 sc0 ls0 ws0"> </div><div class="t m0 xc h9 y22 ff5 fs5 fc1 sc0 ls0 ws0">Technical Support<span class="ff4"> </span></div><div class="t m0 xc h9 y23 ff4 fs5 fc1 sc0 ls9 ws0">techsupp@pcisig.com </div><div class="t m0 xd hb y24 ff4 fs3 fc1 sc0 ls0 ws0"> </div><div class="t m0 xe hc y25 ff3 fs5 fc1 sc0 ls10 ws0">DISCLAIMER </div><div class="t m0 xf h9 y26 ff4 fs5 fc1 sc0 ls0 ws0">This PCI Express Base Specification is prov<span class="lsa wsb">ided “as is” with no warranties whatsoever, </span></div><div class="t m0 xf h9 y27 ff4 fs5 fc1 sc0 ls9 ws9">including any warranty of merchantability, noninfringement, fitness for any particular </div><div class="t m0 xf h9 y28 ff4 fs5 fc1 sc0 ls9 ws14">purpose, or any warranty otherwise arising ou<span class="ls0 ws0">t of any proposal, specification, or sample. </span></div><div class="t m0 xf h9 y29 ff4 fs5 fc1 sc0 ls0 ws0">PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of </div><div class="t m0 xf h9 y2a ff4 fs5 fc1 sc0 ls0 ws0">information in this specification. No li<span class="ls9 ws9">cense, express or implied, by estoppel or </span></div><div class="t m0 xf h9 y2b ff4 fs5 fc1 sc0 lsa wse">otherwise, to any intellectual property rights is granted herein. </div><div class="t m0 x9 h9 y2c ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y2d ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y2e ff4 fs5 fc1 sc0 ls11 ws15">PCI Express and PCI-SIG are trademarks of PCI-SIG. </div><div class="t m0 x9 h9 y2f ff4 fs5 fc1 sc0 ls9 ws14">All other product names are trademarks, registered <span class="lsa wse">trademarks, or servicemarks of their respective </span></div><div class="t m0 x9 h9 y30 ff4 fs5 fc1 sc0 lsd ws0">owners. </div><div class="t m0 x9 h9 y31 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y32 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y33 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y34 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y35 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x10 h9 y36 ff4 fs5 fc1 sc0 lsd ws16">Copyright © 2002-2005 PCI-SIG </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/bg3.jpg"><div class="t m0 x11 h2 y37 ff1 fs0 fc0 sc0 ls12 ws17">PCI EXPRESS BASE SPECIFICATION, REV 1.1 </div><div class="t m0 x9 h2 y38 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _10"> </span><span class="ls5">3 </span></div><div class="t m0 x12 h9 y39 ff4 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h4 y3a ff2 fs2 fc0 sc0 ls13 ws0">Contents </div><div class="t m0 x9 hd y3b ff6 fs5 fc1 sc0 lsa ws18">OBJECTIVE OF THE SPECIFICATION<span class="_ _11"></span>....................................................................................<span class="_ _12"> </span>19 </div><div class="t m0 x9 hd y3c ff6 fs5 fc1 sc0 lsa wse">DOCUMENT ORGANIZATION<span class="_"> </span>................................................................................................<span class="_ _12"> </span>19 </div><div class="t m0 x9 hd y3d ff6 fs5 fc1 sc0 ls9 ws19">DOCUMENTATION CONVENTIONS<span class="_ _13"> </span>......................................................................................<span class="_ _12"> </span>20 </div><div class="t m0 x9 hd y3e ff6 fs5 fc1 sc0 ls0 ws0">TERMS AND ACRONYMS<span class="_ _14"></span>........................................................................................................<span class="_ _12"> </span>21 </div><div class="t m0 x9 hd y3f ff6 fs5 fc1 sc0 lsa wse">REFERENCE DOCUMENTS<span class="_ _11"></span>......................................................................................................<span class="_ _12"> </span>26 </div><div class="t m0 x9 hd y40 ff6 fs5 fc1 sc0 ls0 ws1a">1. INTRODUCTION<span class="_ _12"> </span>................................................................................................................<span class="_ _12"> </span><span class="ws0">27 </span></div><div class="t m0 x13 hd y41 ff6 fs5 fc1 sc0 ls14 ws1b">1.1. A <span class="_ _15"></span>T</div><div class="t m0 x14 hd y42 ff6 fs6 fc1 sc0 ls15 ws0">HIRD <span class="fs5 ls0">G</span><span class="ls16">ENERATION <span class="fs5 lsa wse">I/O I</span><span class="ls17">NTERCONNECT<span class="_ _13"> </span><span class="fs5 ls0">...................................................................<span class="_ _12"> </span>27 </span></span></span></div><div class="t m0 x13 hd y43 ff6 fs5 fc1 sc0 lsd ws1c">1.2. PCI <span class="_ _15"></span>E<span class="fs6 ls18 ws0">XPRESS <span class="fs5 ls0">L</span><span class="ls19">INK<span class="_"> </span><span class="fs5 ls0">........................................................................................................<span class="_"> </span>29 </span></span></span></div><div class="t m0 x13 hd y44 ff6 fs5 fc1 sc0 lsd ws1c">1.3. PCI <span class="_ _15"></span>E<span class="fs6 ls18 ws0">XPRESS <span class="fs5 ls0">F</span><span class="ls1a">ABRIC <span class="fs5 ls0">T</span><span class="ls1b">O<span class="_ _1"></span>POLOGY<span class="_ _16"> </span><span class="fs5 ls0">..................................................................................<span class="_ _12"> </span>30 </span></span></span></span></div><div class="t m0 x15 hd y45 ff7 fs5 fc1 sc0 ls0 ws0">1.3.1.<span class="ff6"> <span class="_ _17"> </span></span>Root Complex<span class="_ _11"></span>........................................................................................................<span class="_ _12"> </span>30<span class="ff6"> </span></div><div class="t m0 x15 hd y46 ff7 fs5 fc1 sc0 ls0 ws0">1.3.2.<span class="ff6"> <span class="_ _17"> </span></span>Endpoints<span class="_ _12"> </span>..............................................................................................................<span class="_ _12"> </span>31<span class="ff6"> </span></div><div class="t m0 x15 hd y47 ff7 fs5 fc1 sc0 ls0 ws0">1.3.3.<span class="ff6"> <span class="_ _17"> </span></span>Switch<span class="_ _14"></span>....................................................................................................................<span class="_ _12"> </span>34<span class="ff6"> </span></div><div class="t m0 x15 hd y48 ff7 fs5 fc1 sc0 ls0 ws0">1.3.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Root Complex Event Collector..............................................................................<span class="_ _12"> </span>35</span><span class="ff6"> </span></div><div class="t m0 x15 hd y49 ff7 fs5 fc1 sc0 ls0 ws0">1.3.5.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">PCI Express-PCI Bridge<span class="_ _11"></span>.......................................................................................<span class="_ _12"> </span>35</span><span class="ff6"> </span></div><div class="t m0 x13 hd y4a ff6 fs5 fc1 sc0 lsd ws1c">1.4. PCI <span class="_ _15"></span>E<span class="fs6 ls18 ws0">XPRESS <span class="fs5 ls0">F</span><span class="ls1a">ABRIC <span class="fs5 ls0">T<span class="fs6">O<span class="_ _1"></span>POLOGY </span>C</span><span class="ls1c">ONFIGU<span class="_ _2"></span>RATION<span class="_ _11"></span><span class="fs5 ls0">.......................................................<span class="_ _12"> </span>35 </span></span></span></span></div><div class="t m0 x13 hd y4b ff6 fs5 fc1 sc0 lsd ws1c">1.5. PCI <span class="_ _15"></span>E<span class="fs6 ls18 ws0">XPRESS <span class="fs5 ls0">L</span><span class="ls1b">AYERING <span class="fs5 ls0">O</span><span class="ls1d">VERVIEW<span class="_ _18"> </span><span class="fs5 ls0">.............................................................................<span class="_ _12"> </span>36 </span></span></span></span></div><div class="t m0 x15 hd y4c ff7 fs5 fc1 sc0 ls0 ws0">1.5.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws1d">Transaction Layer<span class="_ _14"></span>.................................................................................................<span class="_ _12"> </span>37</span><span class="ff6"> </span></div><div class="t m0 x15 hd y4d ff7 fs5 fc1 sc0 ls0 ws0">1.5.2.<span class="ff6"> <span class="_ _17"> </span></span>Data Link Layer<span class="_ _13"> </span>....................................................................................................<span class="_ _12"> </span>37<span class="ff6"> </span></div><div class="t m0 x15 hd y4e ff7 fs5 fc1 sc0 ls0 ws0">1.5.3.<span class="ff6"> <span class="_ _17"> </span></span>Physical Layer<span class="_ _12"> </span>......................................................................................................<span class="_ _12"> </span>38<span class="ff6"> </span></div><div class="t m0 x15 hd y4f ff7 fs5 fc1 sc0 ls0 ws0">1.5.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Layer Functions and Services<span class="_ _14"></span>...............................................................................<span class="_ _12"> </span>38</span><span class="ff6"> </span></div><div class="t m0 x9 hd y50 ff6 fs5 fc1 sc0 lsa wse">2. <span class="_ _19"> </span>TRANSACTION LAYER SPECIFICATION<span class="_ _12"> </span>.....................................................................<span class="_ _12"> </span>43 </div><div class="t m0 x13 hd y51 ff6 fs5 fc1 sc0 ls0 ws1e">2.1. T</div><div class="t m0 x16 hd y52 ff6 fs6 fc1 sc0 ls1e ws0">RANSACTION <span class="fs5 ls0">L</span><span class="ls1f">AYER <span class="fs5 ls0">O</span><span class="ls1d">VERVIEW<span class="_ _1"></span><span class="fs5 ls0">..................................................................................<span class="_ _12"> </span>43 </span></span></span></div><div class="t m0 x15 hd y53 ff7 fs5 fc1 sc0 ls0 ws0">2.1.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="ws1f">Address Spaces, Transaction Types, and Usage<span class="_ _1"></span>...................................................<span class="_ _12"> </span>44</span><span class="ff6"> </span></div><div class="t m0 x15 hd y54 ff7 fs5 fc1 sc0 ls0 ws0">2.1.2.<span class="ff6"> <span class="_ _17"> </span></span>Packet Format Overview<span class="_ _12"> </span>......................................................................................<span class="_ _12"> </span>46<span class="ff6"> </span></div><div class="t m0 x13 hd y55 ff6 fs5 fc1 sc0 ls0 ws1e">2.2. T<span class="fs6 ls1e ws0">RANSACTION </span><span class="ws0">L<span class="fs6 ls1f">AYER </span>P<span class="fs6 ls20">ROT<span class="_ _1"></span>OCOL </span><span class="ls21 ws20">- P</span><span class="fs6 ls16">ACKET </span>D<span class="fs6 ls22">EFINITION</span>...............................................<span class="_"> </span>47 </span></div><div class="t m0 x15 hd y56 ff7 fs5 fc1 sc0 ls0 ws0">2.2.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws16">Common Packet Header Fields<span class="_ _16"> </span>............................................................................<span class="_ _12"> </span>47</span><span class="ff6"> </span></div><div class="t m0 x15 hd y57 ff7 fs5 fc1 sc0 ls0 ws0">2.2.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">TLPs with Data Payloads - Rules<span class="_ _13"> </span>.........................................................................<span class="_ _12"> </span>50</span><span class="ff6"> </span></div><div class="t m0 x15 hd y58 ff7 fs5 fc1 sc0 ls0 ws0">2.2.3.<span class="ff6"> <span class="_ _17"> </span></span>TLP Digest Rules<span class="_ _12"> </span>..................................................................................................<span class="_ _12"> </span>52<span class="ff6"> </span></div><div class="t m0 x15 hd y59 ff7 fs5 fc1 sc0 ls0 ws0">2.2.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws16">Routing and Addressing Rules<span class="_ _13"></span>..............................................................................<span class="_ _12"> </span>52</span><span class="ff6"> </span></div><div class="t m0 x15 hd y5a ff7 fs5 fc1 sc0 ls0 ws0">2.2.5.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">First/Last DW Byte Enables Rules<span class="_ _1"></span>........................................................................<span class="_ _12"> </span>55</span><span class="ff6"> </span></div><div class="t m0 x15 hd y5b ff7 fs5 fc1 sc0 ls0 ws0">2.2.6.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws1d">Transaction Descriptor<span class="_ _11"></span>.........................................................................................<span class="_"> </span>57</span><span class="ff6"> </span></div><div class="t m0 x15 hd y5c ff7 fs5 fc1 sc0 ls0 ws0">2.2.7.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Memory, I/O, and Configuration Request Rules<span class="_ _1"></span>...................................................<span class="_ _12"> </span>62</span><span class="ff6"> </span></div><div class="t m0 x15 hd y5d ff7 fs5 fc1 sc0 ls0 ws0">2.2.8.<span class="ff6"> <span class="_ _17"> </span></span>Message Request Rules<span class="_ _13"></span>.........................................................................................<span class="_ _12"> </span>65<span class="ff6"> </span></div><div class="t m0 x15 hd y5e ff7 fs5 fc1 sc0 ls0 ws0">2.2.9.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws1d">Completion Rules<span class="_ _13"></span>..................................................................................................<span class="_ _12"> </span>76<span class="_ _2"></span><span class="ff6 ls0 ws0"> </span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/bg4.jpg"><div class="t m0 x11 h2 y37 ff1 fs0 fc0 sc0 ls12 ws17">PCI EXPRESS BASE SPECIFICATION, REV 1.1 </div><div class="t m0 x9 h2 y38 ff1 fs0 fc0 sc0 ls5 ws0">4 </div><div class="t m0 x13 hd y5f ff6 fs5 fc1 sc0 ls0 ws21">2.3. H<span class="fs6 ls23 ws22">ANDLING OF </span><span class="ws0">R<span class="fs6 ls22">ECEIVED </span><span class="ls24">TLP</span><span class="fs6">S<span class="_ _1"></span></span>......................................................................................<span class="_ _12"> </span>78 </span></div><div class="t m0 x15 hd y60 ff7 fs5 fc1 sc0 ls0 ws0">2.3.1.<span class="ff6"> <span class="_ _17"> </span></span>Request Handling Rules<span class="_ _14"></span>........................................................................................<span class="_ _12"> </span>81<span class="ff6"> </span></div><div class="t m0 x15 hd y61 ff7 fs5 fc1 sc0 ls0 ws0">2.3.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws23">Completion Handling Rules<span class="_ _14"></span>..................................................................................<span class="_ _12"> </span>93</span><span class="ff6"> </span></div><div class="t m0 x13 hd y62 ff6 fs5 fc1 sc0 ls0 ws1e">2.4. T</div><div class="t m0 x16 hd y63 ff6 fs6 fc1 sc0 ls1e ws0">RANSACTION <span class="fs5 ls0">O</span><span class="ls25">RDERING<span class="_ _13"> </span><span class="fs5 ls0">..............................................................................................<span class="_ _12"> </span>95 </span></span></div><div class="t m0 x15 hd y64 ff7 fs5 fc1 sc0 ls0 ws0">2.4.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws23">Transaction Ordering Rules<span class="_ _12"> </span>.................................................................................<span class="_ _12"> </span>95</span><span class="ff6"> </span></div><div class="t m0 x15 hd y65 ff7 fs5 fc1 sc0 ls0 ws0">2.4.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Update Ordering and Granularity Observed by a Read Transaction<span class="_ _13"> </span>..................<span class="_ _12"> </span>99</span><span class="ff6"> </span></div><div class="t m0 x15 hd y66 ff7 fs5 fc1 sc0 ls0 ws0">2.4.3.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Update Ordering and Granularity Provided by a Write Transaction<span class="_ _13"> </span>................<span class="_ _12"> </span>100</span><span class="ff6"> </span></div><div class="t m0 x13 hd y67 ff6 fs5 fc1 sc0 ls0 ws1e">2.5. V</div><div class="t m0 x17 hd y68 ff6 fs6 fc1 sc0 ls1d ws0">IRTUAL <span class="fs5 ls0">C</span><span class="ls15">HANNEL <span class="fs5 ls0">(VC) M</span><span class="ls23">ECHANISM<span class="_ _18"> </span><span class="fs5 ls0">.......................................................................<span class="_ _12"> </span>100 </span></span></span></div><div class="t m0 x15 hd y69 ff7 fs5 fc1 sc0 ls0 ws0">2.5.1.<span class="ff6"> <span class="_ _17"> </span></span>Virtual Channel Identification (VC ID)<span class="_ _13"> </span>..............................................................<span class="_ _12"> </span>103<span class="ff6"> </span></div><div class="t m0 x15 hd y6a ff7 fs5 fc1 sc0 ls0 ws0">2.5.2.<span class="ff6"> <span class="_ _17"> </span></span>TC to VC Mapping<span class="_ _13"></span>..............................................................................................<span class="_ _12"> </span>103<span class="ff6"> </span></div><div class="t m0 x15 hd y6b ff7 fs5 fc1 sc0 ls0 ws0">2.5.3.<span class="ff6"> <span class="_ _17"> </span></span><span class="ws24">VC and TC Rules<span class="_ _1"></span>.................................................................................................<span class="_ _12"> </span>105</span><span class="ff6"> </span></div><div class="t m0 x13 hd y6c ff6 fs5 fc1 sc0 ls0 ws1e">2.6. O<span class="fs6 ls26 ws25">RDERING AND </span><span class="ws0">R<span class="fs6 ls27">ECEIVE </span>B<span class="fs6 ls28">UFFER </span>F<span class="fs6 ls29">LOW </span>C<span class="fs6 ls1e">ONTROL<span class="_"> </span></span>.....................................................<span class="_ _12"> </span>106 </span></div><div class="t m0 x15 hd y6d ff7 fs5 fc1 sc0 ls0 ws0">2.6.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Flow Control Rules<span class="_ _13"></span>.............................................................................................<span class="_ _12"> </span>107<span class="_ _2"></span><span class="ff6 ls0 ws0"> </span></span></div><div class="t m0 x13 hd y6e ff6 fs5 fc1 sc0 ls0 ws1e">2.7. D</div><div class="t m0 x17 hd y6f ff6 fs6 fc1 sc0 ls2a ws0">ATA <span class="fs5 ls0">I</span><span class="ls2b">NTEGRITY<span class="_ _16"> </span><span class="fs5 ls0">.........................................................................................................<span class="_ _12"> </span>116 </span></span></div><div class="t m0 x15 hd y70 ff7 fs5 fc1 sc0 ls0 ws0">2.7.1.<span class="ff6"> <span class="_ _17"> </span></span>ECRC Rules<span class="_ _12"> </span>........................................................................................................<span class="_ _12"> </span>117<span class="ff6"> </span></div><div class="t m0 x15 hd y71 ff7 fs5 fc1 sc0 ls0 ws0">2.7.2.<span class="ff6"> <span class="_ _17"> </span></span>Error Forwarding<span class="_ _13"> </span>...............................................................................................<span class="_ _12"> </span>121<span class="ff6"> </span></div><div class="t m0 x13 hd y72 ff6 fs5 fc1 sc0 ls0 ws1e">2.8. C</div><div class="t m0 x18 hd y73 ff6 fs6 fc1 sc0 ls2c ws0">OMPLETION <span class="fs5 ls0">T</span><span class="ls22">IMEOUT <span class="fs5 ls0">M</span><span class="ls18">ECHANISM<span class="_ _16"> </span><span class="fs5 ls0">...........................................................................<span class="_ _12"> </span>123 </span></span></span></div><div class="t m0 x13 hd y74 ff6 fs5 fc1 sc0 ls0 ws1e">2.9. L<span class="fs6 ls18 ws0">INK </span><span class="ws0">S<span class="fs6 ls2d">TATUS </span>D<span class="fs6 ls15">EPENDENCIES<span class="_"> </span></span>......................................................................................<span class="_ _12"> </span>124 </span></div><div class="t m0 x15 hd y75 ff7 fs5 fc1 sc0 ls0 ws0">2.9.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws26">Transaction Layer Behavior in DL_Down Status<span class="_ _1"></span>...............................................<span class="_ _12"> </span>124</span><span class="ff6"> </span></div><div class="t m0 x15 hd y76 ff7 fs5 fc1 sc0 ls0 ws0">2.9.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws26">Transaction Layer Behavior in DL_Up Status<span class="_ _12"> </span>...................................................<span class="_ _12"> </span>125</span><span class="ff6"> </span></div><div class="t m0 x9 hd y77 ff6 fs5 fc1 sc0 lsa ws18">3. <span class="_ _19"> </span>DATA LINK LAYER SPECIFICATION<span class="_ _13"></span>..........................................................................<span class="_ _12"> </span>127 </div><div class="t m0 x13 hd y78 ff6 fs5 fc1 sc0 ls0 ws1e">3.1. D<span class="fs6 ls2a ws0">ATA </span><span class="ws0">L<span class="fs6 ls18">INK </span>L<span class="fs6 ls1f">AYER </span>O<span class="fs6 ls1d">VERVIEW<span class="_ _16"> </span></span>....................................................................................<span class="_ _12"> </span>127 </span></div><div class="t m0 x13 hd y79 ff6 fs5 fc1 sc0 ls0 ws1e">3.2. D<span class="fs6 ls2a ws0">ATA </span><span class="ws0">L<span class="fs6 ls18">INK </span>C<span class="fs6 ls1d ws27">ONTROL AND </span>M<span class="fs6 ls28">ANAGEMENT </span>S<span class="fs6 ls2e">TATE </span>M<span class="fs6 ls2f">ACHINE<span class="_ _18"> </span></span>......................................<span class="_ _12"> </span>129 </span></div><div class="t m0 x15 hd y7a ff7 fs5 fc1 sc0 ls0 ws0">3.2.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls30 ws28">Data Link Control and Management State Machine Rules<span class="_ _16"> </span>................................<span class="_ _12"> </span>130</span><span class="ff6"> </span></div><div class="t m0 x13 hd y7b ff6 fs5 fc1 sc0 ls0 ws1e">3.3. F<span class="fs6 ls31 ws0">LOW </span><span class="ws0">C<span class="fs6 ls32">ONTROL </span>I<span class="fs6 ls19">NITIALIZATION </span>P<span class="fs6 ls33">ROTOCOL<span class="_"> </span></span>...............................................................<span class="_ _12"> </span>132 </span></div><div class="t m0 x15 hd y7c ff7 fs5 fc1 sc0 ls0 ws0">3.3.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Flow Control Initializati</span>on State Machine Rules<span class="_ _12"> </span>...............................................<span class="_ _12"> </span>132<span class="ff6"> </span></div><div class="t m0 x13 hd y7d ff6 fs5 fc1 sc0 ls0 ws1e">3.4. D<span class="fs6 ls2a ws0">ATA </span><span class="ws0">L<span class="fs6 ls18">INK </span>L<span class="fs6 ls1f">AYER </span>P<span class="fs6 ls34">ACKETS </span><span class="lsb">(DLLP</span><span class="fs6">S</span>)<span class="_ _14"></span>........................................................................<span class="_ _12"> </span>136 </span></div><div class="t m0 x15 hd y7e ff7 fs5 fc1 sc0 ls0 ws0">3.4.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws29">Data Link Layer Packet Rules<span class="_ _12"> </span>............................................................................<span class="_ _12"> </span>136</span><span class="ff6"> </span></div><div class="t m0 x13 hd y7f ff6 fs5 fc1 sc0 ls0 ws1e">3.5. D<span class="fs6 ls2a ws0">ATA </span><span class="ws0">I<span class="fs6 ls2b">NTEGRITY<span class="_ _16"> </span></span>.........................................................................................................<span class="_ _12"> </span>141 </span></div><div class="t m0 x15 hd y80 ff7 fs5 fc1 sc0 ls0 ws0">3.5.1.<span class="ff6"> <span class="_ _17"> </span></span>Introduction.........................................................................................................<span class="_ _12"> </span>141<span class="ff6"> </span></div><div class="t m0 x15 hd y81 ff7 fs5 fc1 sc0 ls0 ws0">3.5.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lse ws10">LCRC, Sequence Number, and Retry <span class="ls30 ws2a">Management (TLP Transmitter)..............<span class="_ _12"> </span>141</span></span><span class="ff6"> </span></div><div class="t m0 x15 hd y82 ff7 fs5 fc1 sc0 ls0 ws0">3.5.3.<span class="ff6"> <span class="_ _17"> </span></span><span class="ws14">LCRC and Sequence Number (TLP Receiver)<span class="_ _13"></span>....................................................<span class="_ _12"> </span>153</span><span class="ff6"> </span></div><div class="t m0 x9 hd y83 ff6 fs5 fc1 sc0 lsa wse">4. <span class="_ _19"> </span>PHYSICAL LAYER SPECIFICATION<span class="_ _13"> </span>............................................................................<span class="_ _12"> </span>161 </div><div class="t m0 x13 hd y84 ff6 fs5 fc1 sc0 ls0 ws1e">4.1. I</div><div class="t m0 x19 hd y85 ff6 fs6 fc1 sc0 ls1b ws0">NTRODUCTION<span class="_"> </span><span class="fs5 ls0">............................................................................................................<span class="_ _12"> </span>161 </span></div><div class="t m0 x13 hd y86 ff6 fs5 fc1 sc0 ls0 ws1e">4.2. L<span class="fs6 ls35 ws0">OGICAL </span><span class="ws0">S<span class="fs6 ls36">UB</span>-<span class="fs6 ls20">BLOCK<span class="_ _1"></span></span>...................................................................................................<span class="_ _12"> </span>161 </span></div><div class="t m0 x15 hd y87 ff7 fs5 fc1 sc0 ls0 ws0">4.2.1.<span class="ff6"> <span class="_ _17"> </span></span>Symbol Encoding<span class="_ _12"> </span>................................................................................................<span class="_ _12"> </span>162<span class="ff6"> </span></div><div class="t m0 x15 hd y88 ff7 fs5 fc1 sc0 ls0 ws0">4.2.2.<span class="ff6"> <span class="_ _17"> </span></span>Framing and Application of Symbols to Lanes<span class="_ _11"></span>...................................................<span class="_ _12"> </span>165<span class="ff6"> </span></div><div class="t m0 x15 hd y89 ff7 fs5 fc1 sc0 ls0 ws0">4.2.3.<span class="ff6"> <span class="_ _17"> </span></span>Data Scrambling<span class="_ _13"> </span>.................................................................................................<span class="_ _12"> </span>168<span class="ff6"> </span></div><div class="t m0 x15 hd y8a ff7 fs5 fc1 sc0 ls0 ws0">4.2.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Link Initialization and Training<span class="_ _1"></span>..........................................................................<span class="_ _12"> </span>169</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8b ff7 fs5 fc1 sc0 ls0 ws0">4.2.5.<span class="ff6"> <span class="_ _17"> </span></span><span class="lse ws10">Link Training and Status State </span><span class="ws2b">Machine (LTSSM) Descriptions<span class="_ _1"></span>........................<span class="_ _12"> </span>177</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8c ff7 fs5 fc1 sc0 ls0 ws0">4.2.6.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Link Training and Status State Rules<span class="_ _1"></span>..................................................................<span class="_ _12"> </span>180</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8d ff7 fs5 fc1 sc0 ls0 ws0">4.2.7.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Clock Tolerance Compensation<span class="_ _14"></span>..........................................................................<span class="_ _12"> </span>210</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8e ff7 fs5 fc1 sc0 ls0 ws0">4.2.8.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws1d">Compliance Pattern<span class="_ _16"> </span>............................................................................................<span class="_ _12"> </span>211</span><span class="ff6"> </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625107416caf59619235e3bc/bg5.jpg"><div class="t m0 x11 h2 y37 ff1 fs0 fc0 sc0 ls12 ws17">PCI EXPRESS BASE SPECIFICATION, REV 1.1 </div><div class="t m0 x9 h2 y38 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _10"> </span><span class="ls5">5 </span></div><div class="t m0 x13 hd y5f ff6 fs5 fc1 sc0 ls0 ws21">4.3. E<span class="fs6 ls37 ws0">LECTRICAL </span><span class="ws0">S<span class="fs6 ls38">UB</span>-<span class="fs6 ls39">BLOCK<span class="_"> </span></span>.............................................................................................<span class="_ _12"> </span>213 </span></div><div class="t m0 x15 hd y60 ff7 fs5 fc1 sc0 ls0 ws0">4.3.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Electrical Sub-Block Requirements<span class="_ _12"> </span>....................................................................<span class="_ _12"> </span>213<span class="_ _2"></span><span class="ff6 ls0 ws0"> </span></span></div><div class="t m0 x15 hd y61 ff7 fs5 fc1 sc0 ls0 ws0">4.3.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Electrical Signal Specifications<span class="_ _13"> </span>..........................................................................<span class="_ _12"> </span>217</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8f ff7 fs5 fc1 sc0 ls0 ws0">4.3.3.<span class="ff6"> <span class="_ _17"> </span></span><span class="lse ws2c">Differential Transmitter (TX) Output Specifications<span class="_ _13"> </span>..........................................<span class="_ _12"> </span>222</span><span class="ff6"> </span></div><div class="t m0 x15 hd y90 ff7 fs5 fc1 sc0 ls0 ws0">4.3.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls11 ws2d">Differential Receiver (RX) Input Specifications<span class="_ _12"> </span>.................................................<span class="_ _12"> </span>228</span><span class="ff6"> </span></div><div class="t m0 x9 hd y91 ff6 fs5 fc1 sc0 lsa ws2e">5. POWER <span class="_ _1a"></span>MANAGEMENT<span class="_ _1"></span>.................................................................................................<span class="_ _12"> </span>231 </div><div class="t m0 x13 hd y92 ff6 fs5 fc1 sc0 ls0 ws1e">5.1. O<span class="fs6 ls1d ws0">VERVIEW<span class="_ _13"> </span></span><span class="ws0">...................................................................................................................<span class="_ _12"> </span>231 </span></div><div class="t m0 x15 hd y93 ff7 fs5 fc1 sc0 ls0 ws0">5.1.1.<span class="ff6"> <span class="_ _17"> </span></span>Statement of Requirements<span class="_ _1"></span>..................................................................................<span class="_ _12"> </span>232<span class="ff6"> </span></div><div class="t m0 x13 hd y94 ff6 fs5 fc1 sc0 ls0 ws1e">5.2. L</div><div class="t m0 x16 hd y95 ff6 fs6 fc1 sc0 ls18 ws0">INK <span class="fs5 ls0">S</span><span class="ls27">TATE <span class="fs5 ls0">P</span><span class="ls28">OWER <span class="fs5 ls0">M</span>ANAGEMENT<span class="_ _1"></span><span class="fs5 ls0">.............................................................................<span class="_ _12"> </span>232 </span></span></span></div><div class="t m0 x13 hd y96 ff6 fs5 fc1 sc0 lsd ws1c">5.3. PCI-PM <span class="_ _15"></span>S</div><div class="t m0 x1a hd y97 ff6 fs6 fc1 sc0 ls2f ws0">OFTWARE <span class="fs5 ls0">C</span><span class="ls35">OMPATIBLE <span class="fs5 ls0">M</span><span class="ls18">ECHANISMS<span class="_ _18"> </span><span class="fs5 ls0">........................................................<span class="_ _12"> </span>237 </span></span></span></div><div class="t m0 x15 hd y98 ff7 fs5 fc1 sc0 ls0 ws0">5.3.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lse ws10">Device Power Management States (D-States) of a Function..............................<span class="_ _12"> </span>237</span><span class="ff6"> </span></div><div class="t m0 x15 hd y99 ff7 fs5 fc1 sc0 ls0 ws0">5.3.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls30 ws2f">PM Software Control of the Li</span>nk Power Management State<span class="_ _1"></span>..............................<span class="_ _12"> </span>241<span class="ff6"> </span></div><div class="t m0 x15 hd y9a ff7 fs5 fc1 sc0 ls0 ws0">5.3.3.<span class="ff6"> <span class="_ _17"> </span></span>Power Management Event Mechanisms<span class="_ _13"> </span>.............................................................<span class="_"> </span>246<span class="_ _2"></span><span class="ff6"> </span></div><div class="t m0 x13 hd y9b ff6 fs5 fc1 sc0 ls0 ws1e">5.4. N</div><div class="t m0 x17 hd y9c ff6 fs6 fc1 sc0 ls3a ws0">ATIVE <span class="fs5 ls30 ws2a">PCI E</span><span class="ls23">XPRESS <span class="fs5 ls0">P</span><span class="ls3b">OWER <span class="fs5 ls0">M</span><span class="ls16">ANAGEMENT <span class="fs5 ls0">M</span></span></span></span>ECHANISMS<span class="_ _1"></span><span class="fs5 ls0">.......................................<span class="_ _12"> </span>253 </span></div><div class="t m0 x15 hd y9d ff7 fs5 fc1 sc0 ls0 ws0">5.4.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws29">Active State Power Management (ASPM)<span class="_ _12"> </span>..........................................................<span class="_ _12"> </span>253</span><span class="ff6"> </span></div><div class="t m0 x13 hd y9e ff6 fs5 fc1 sc0 ls0 ws1e">5.5. A</div><div class="t m0 x17 hd y9f ff6 fs6 fc1 sc0 ls3c ws0">UXILIARY <span class="fs5 ls0">P</span><span class="ls1f">OWER <span class="fs5 ls0">S</span><span class="ls3d">UPPORT<span class="_ _14"> </span><span class="fs5 ls0">.......................................................................................<span class="_ _12"> </span>269 </span></span></span></div><div class="t m0 x15 hd ya0 ff7 fs5 fc1 sc0 ls0 ws0">5.5.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls30 ws2a">Auxiliary Power Enabling...................................................................................<span class="_ _12"> </span>269<span class="_ _2"></span><span class="ff6 ls0 ws0"> </span></span></div><div class="t m0 x13 hd ya1 ff6 fs5 fc1 sc0 ls0 ws1e">5.6. P<span class="fs6 ls28 ws0">OWER </span><span class="ws0">M<span class="fs6 ls2a">ANAGEMENT </span>S<span class="fs6 ls2b">YSTEM </span>M<span class="fs6 ls23 ws22">ESSAGES AND </span><span class="ls3e">DLLP</span><span class="fs6">S<span class="_ _1"></span></span>.............................................<span class="_ _12"> </span>270 </span></div><div class="t m0 x9 hd ya2 ff6 fs5 fc1 sc0 lsa ws2e">6. SYSTEM <span class="_ _1a"></span>ARCHITECTURE<span class="_ _12"> </span>.............................................................................................<span class="_ _12"> </span>273 </div><div class="t m0 x13 hd ya3 ff6 fs5 fc1 sc0 ls0 ws1e">6.1. I<span class="fs6 ls3f ws30">NTERRUPT AND </span><span class="lsb ws31">PME S<span class="fs6 ls3d ws0">UPPORT<span class="_ _14"></span></span></span><span class="ws0">...................................................................................<span class="_ _12"> </span>273 </span></div><div class="t m0 x15 hd ya4 ff7 fs5 fc1 sc0 ls0 ws0">6.1.1.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsf ws32">Rationale for PCI Expre</span><span class="ws33">ss Interrupt Model........................................................<span class="_ _12"> </span>273</span><span class="ff6"> </span></div><div class="t m0 x15 hd ya5 ff7 fs5 fc1 sc0 ls0 ws0">6.1.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="ws2d">PCI Compatible INTx Emulation<span class="_ _11"></span>........................................................................<span class="_ _12"> </span>274</span><span class="ff6"> </span></div><div class="t m0 x15 hd ya6 ff7 fs5 fc1 sc0 ls0 ws0">6.1.3.<span class="ff6"> <span class="_ _17"> </span></span>INTx Emulation Software Model<span class="_ _12"> </span>........................................................................<span class="_ _12"> </span>274<span class="ff6"> </span></div><div class="t m0 x15 hd ya7 ff7 fs5 fc1 sc0 ls0 ws0">6.1.4.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls30 ws2a">Message Signaled Interrupt (MSI/MSI-X) Support.............................................<span class="_ _12"> </span>274</span><span class="ff6"> </span></div><div class="t m0 x15 hd ya8 ff7 fs5 fc1 sc0 ls0 ws0">6.1.5.<span class="ff6"> <span class="_ _17"> </span></span>PME Support<span class="_ _1"></span>.......................................................................................................<span class="_ _12"> </span>276<span class="ff6"> </span></div><div class="t m0 x15 hd ya9 ff7 fs5 fc1 sc0 ls0 ws0">6.1.6.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Native PME Software Model<span class="_ _12"> </span>..............................................................................<span class="_ _12"> </span>276</span><span class="ff6"> </span></div><div class="t m0 x15 hd yaa ff7 fs5 fc1 sc0 ls0 ws0">6.1.7.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws16">Legacy PME Software Model<span class="_ _12"> </span>.............................................................................<span class="_ _12"> </span>277</span><span class="ff6"> </span></div><div class="t m0 x15 hd yab ff7 fs5 fc1 sc0 ls0 ws0">6.1.8.<span class="ff6"> <span class="_ _17"> </span></span>Operating System Power Management Notification...........................................<span class="_ _12"> </span>277<span class="ff6"> </span></div><div class="t m0 x15 hd yac ff7 fs5 fc1 sc0 ls0 ws0">6.1.9.<span class="ff6"> <span class="_ _17"> </span></span><span class="ls30 ws28">PME Routing Between PCI Express and PCI Hierarchies<span class="_ _12"> </span>................................<span class="_ _12"> </span>277</span><span class="ff6"> </span></div><div class="t m0 x13 hd yad ff6 fs5 fc1 sc0 ls0 ws1e">6.2. E</div><div class="t m0 x16 hd yae ff6 fs6 fc1 sc0 ls33 ws0">RROR <span class="fs5 ls0">S</span><span class="ls2a ws34">IGNALING AND <span class="_ _1"></span></span><span class="fs5 ls0">L</span><span class="ls18">OGGING<span class="fs5 ls0">................................................................................<span class="_ _12"> </span>278 </span></span></div><div class="t m0 x15 hd yaf ff7 fs5 fc1 sc0 ls0 ws0">6.2.1.<span class="ff6"> <span class="_ _17"> </span></span>Scope<span class="_ _13"></span>...................................................................................................................<span class="_ _12"> </span>278<span class="ff6"> </span></div><div class="t m0 x15 hd yb0 ff7 fs5 fc1 sc0 ls0 ws0">6.2.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Error Classification<span class="_ _16"> </span>............................................................................................<span class="_ _12"> </span>278</span><span class="ff6"> </span></div><div class="t m0 x15 hd yb1 ff7 fs5 fc1 sc0 ls0 ws0">6.2.3.<span class="ff6"> <span class="_ _17"> </span></span>Error Signaling<span class="_ _13"> </span>...................................................................................................<span class="_ _12"> </span>280<span class="ff6"> </span></div><div class="t m0 x15 hd yb2 ff7 fs5 fc1 sc0 ls0 ws0">6.2.4.<span class="ff6"> <span class="_ _17"> </span></span>Error Logging<span class="_ _13"> </span>.....................................................................................................<span class="_ _12"> </span>287<span class="ff6"> </span></div><div class="t m0 x15 hd yb3 ff7 fs5 fc1 sc0 ls0 ws0">6.2.5.<span class="ff6"> <span class="_ _17"> </span></span><span class="lse ws35">Sequence of Device Error Signa<span class="lsd ws16">ling and Logging Operations<span class="_ _12"> </span>..........................<span class="_ _12"> </span>290</span></span><span class="ff6"> </span></div><div class="t m0 x15 hd y87 ff7 fs5 fc1 sc0 ls0 ws0">6.2.6.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd wsf">Error Message Controls<span class="_ _12"> </span>.....................................................................................<span class="_ _12"> </span>292</span><span class="ff6"> </span></div><div class="t m0 x15 hd y88 ff7 fs5 fc1 sc0 ls0 ws0">6.2.7.<span class="ff6"> <span class="_ _17"> </span></span>Error Listing and Rules<span class="_ _12"> </span>......................................................................................<span class="_ _12"> </span>293<span class="ff6"> </span></div><div class="t m0 x15 hd y89 ff7 fs5 fc1 sc0 ls0 ws0">6.2.8.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsd ws29">Virtual PCI Bridge Error Handling<span class="_ _1"></span>....................................................................<span class="_ _12"> </span>297</span><span class="ff6"> </span></div><div class="t m0 x13 hd yb4 ff6 fs5 fc1 sc0 ls0 ws1e">6.3. V<span class="fs6 ls1d ws0">IRTUAL </span><span class="ws0">C<span class="fs6 ls15">HANNEL </span>S<span class="fs6 ls40">UPPORT<span class="_ _1b"> </span></span>......................................................................................<span class="_ _12"> </span>298 </span></div><div class="t m0 x15 hd y8b ff7 fs5 fc1 sc0 ls0 ws0">6.3.1.<span class="ff6"> <span class="_ _17"> </span></span>Introduction and Scope<span class="_ _13"></span>.......................................................................................<span class="_ _12"> </span>298<span class="ff6"> </span></div><div class="t m0 x15 hd y8c ff7 fs5 fc1 sc0 ls0 ws0">6.3.2.<span class="ff6"> <span class="_ _17"> </span></span><span class="lsa wse">TC/VC Mapping and Example Usage<span class="_ _11"></span>.................................................................<span class="_ _12"> </span>299</span><span class="ff6"> </span></div><div class="t m0 x15 hd y8d ff7 fs5 fc1 sc0 ls0 ws0">6.3.3.<span class="ff6"> <span class="_ _17"> </span></span>VC Arbitration<span class="_ _12"> </span>....................................................................................................<span class="_ _12"> </span>301<span class="ff6"> </span></div><div class="t m0 x15 hd y8e ff7 fs5 fc1 sc0 ls0 ws0">6.3.4.<span class="ff6"> <span class="_ _17"> </span></span>Isochronous Support<span class="_ _13"> </span>...........................................................................................<span class="_ _12"> </span>309<span class="ff6"> </span></div><div class="t m0 x13 hd yb5 ff6 fs5 fc1 sc0 ls0 ws1e">6.4. D<span class="fs6 ls2e ws0">EVICE </span><span class="ws0">S<span class="fs6 ls28">YNCHRONIZATION<span class="_ _14"></span></span>.........................................................................................<span class="_ _12"> </span>312 </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>