um-sst39VF160.rar_nor flash_SST39VF160_驱动编程

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Data S<span class="_ _0"></span>heet</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">©<span class="_ _0"></span>2002 S<span class="_ _0"></span>ilicon Storage Technology, Inc.</div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">S71145-0<span class="_ _1"></span>2-000<span class="_ _2"> </span>2/02<span class="_ _3"> </span>399</div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls3 ws2">1</div><div class="t m0 x3 h3 y2 ff2 fs1 fc0 sc0 ls4 ws3">The SST logo an<span class="_ _1"></span>d SuperFlash are r<span class="_ _1"></span>egistered tra<span class="_ _1"></span>demarks of Silicon Storage T<span class="_ _4"></span>echnology<span class="_ _4"></span>, Inc.</div><div class="t m0 x4 h3 y3 ff2 fs1 fc0 sc0 ls5 ws4">Multi-Purpose Flash and MPF are trademarks of Silicon Storage T<span class="_ _5"></span>echnology<span class="_ _5"></span>, Inc.</div><div class="t m0 x5 h3 y4 ff2 fs1 fc0 sc0 ls6 ws5">These specif<span class="_ _1"></span>ications are sub<span class="_ _1"></span>ject to change with<span class="_ _1"></span>out notice.</div><div class="t m0 x6 h4 y5 ff3 fs2 fc0 sc0 ls7 ws2">16 Mbit<span class="_ _6"> </span>(x16)<span class="_ _6"> </span>Multi-Purpose Flash</div><div class="t m0 x7 h5 y6 ff3 fs3 fc0 sc0 ls3 ws6">SST39LF160 / SST39VF160</div><div class="t m0 x2 h5 y7 ff3 fs3 fc0 sc0 ls8 ws2">FEATURES:</div><div class="t m0 x2 h2 y8 ff3 fs0 fc0 sc0 ls9 ws7">•<span class="_ _7"> </span>Organized<span class="_ _0"></span> as 1M x1<span class="_ _0"></span>6</div><div class="t m0 x2 h2 y9 ff3 fs0 fc0 sc0 lsa ws8">•<span class="_ _7"> </span>Single V<span class="_ _5"></span>ol<span class="_ _0"></span>tage Read an<span class="_ _0"></span>d Write Op<span class="_ _0"></span>eration<span class="_ _0"></span>s</div><div class="t m0 x8 h6 ya ff2 fs0 fc0 sc0 lsb ws9">–<span class="_ _8"> </span>3.0-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39LF160</div><div class="t m0 x8 h6 yb ff2 fs0 fc0 sc0 lsb ws9">–<span class="_ _8"> </span>2.7-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39VF160</div><div class="t m0 x2 h2 yc ff3 fs0 fc0 sc0 lsc wsa">•<span class="_ _7"> </span>Superior Rel<span class="_ _0"></span>iability</div><div class="t m0 x8 h6 yd ff2 fs0 fc0 sc0 lsd wsb">–<span class="_ _8"> </span>Endurance<span class="_ _0"></span>: 100,000 Cy<span class="_ _0"></span>cles (ty<span class="_ _0"></span>pical)</div><div class="t m0 x8 h6 ye ff2 fs0 fc0 sc0 lse wsc">–<span class="_ _8"> </span>Greater th<span class="_ _0"></span>an 100 years Data<span class="_ _0"></span> Retention</div><div class="t m0 x2 h2 yf ff3 fs0 fc0 sc0 lsf wsd">•<span class="_ _7"> </span>Low P<span class="_ _5"></span>ower Consumption</div><div class="t m0 x8 h6 y10 ff2 fs0 fc0 sc0 ls10 wse">–<span class="_ _8"> </span>Active Current: 15 mA (typical)</div><div class="t m0 x8 h6 y11 ff2 fs0 fc0 sc0 lse wsc">–<span class="_ _8"> </span>Standby Current<span class="_ _0"></span>: 4 µA (typi<span class="_ _0"></span>cal)</div><div class="t m0 x8 h6 y12 ff2 fs0 fc0 sc0 lse wsc">–<span class="_ _8"> </span>A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er Mode<span class="_ _0"></span>: 4 µA (typi<span class="_ _0"></span>cal)</div><div class="t m0 x2 h2 y13 ff3 fs0 fc0 sc0 lsd wsb">•<span class="_ _7"> </span>Sector-Erase<span class="_ _0"></span> Capabil<span class="_ _0"></span>ity</div><div class="t m0 x8 h6 y14 ff2 fs0 fc0 sc0 ls11 wsf">–<span class="_ _8"> </span>Uniform<span class="_ _0"></span> 2 KWord secto<span class="_ _0"></span>rs</div><div class="t m0 x2 h2 y15 ff3 fs0 fc0 sc0 ls12 ws10">•<span class="_ _7"> </span>Fast Read Access<span class="_ _0"></span> Time</div><div class="t m0 x8 h6 y16 ff2 fs0 fc0 sc0 ls13 ws11">–<span class="_ _8"> </span>55 ns f<span class="_ _1"></span>or SST39LF1<span class="_ _0"></span>60</div><div class="t m0 x8 h6 y17 ff2 fs0 fc0 sc0 ls14 ws12">–<span class="_ _8"> </span>70 and 90 ns f<span class="_ _1"></span>or SST39VF160</div><div class="t m0 x2 h2 y18 ff3 fs0 fc0 sc0 ls15 ws13">•<span class="_ _7"> </span>Latched Addr<span class="_ _0"></span>ess and Data</div><div class="t m0 x9 h2 y19 ff3 fs0 fc0 sc0 ls10 ws14">•<span class="_ _7"> </span>Fast Erase and<span class="_ _0"></span> W<span class="_ _1"></span>or<span class="_ _1"></span>d-Program</div><div class="t m0 xa h6 y1a ff2 fs0 fc0 sc0 ls15 ws13">–<span class="_ _8"> </span>Sector-Erase Tim<span class="_ _0"></span>e: 18 m<span class="_ _0"></span>s (typical)</div><div class="t m0 xa h6 y1b ff2 fs0 fc0 sc0 ls16 ws15">–<span class="_ _8"> </span>Blo<span class="_ _0"></span>ck-Eras<span class="_ _0"></span>e Ti<span class="_ _0"></span>me:<span class="_ _0"></span> 18 m<span class="_ _0"></span>s (t<span class="_ _0"></span>ypic<span class="_ _0"></span>al)</div><div class="t m0 xa h6 y1c ff2 fs0 fc0 sc0 ls13 ws16">–<span class="_ _8"> </span>Chip-Era<span class="_ _0"></span>se Time: 70<span class="_ _0"></span> ms (ty<span class="_ _0"></span>pical)</div><div class="t m0 xa h6 y1d ff2 fs0 fc0 sc0 ls13 ws9">–<span class="_ _8"> </span>W<span class="_ _1"></span>ord-P<span class="_ _0"></span>rogram Time: 1<span class="_ _0"></span>4 µs (typic<span class="_ _0"></span>al)</div><div class="t m0 xa h6 y1e ff2 fs0 fc0 sc0 ls13 ws9">–<span class="_ _8"> </span>Chip Rewri<span class="_ _0"></span>te Time: <span class="_ _0"></span>15 seconds<span class="_ _0"></span> (typic<span class="_ _0"></span>al) for </div><div class="t m0 x4 h6 y1f ff2 fs0 fc0 sc0 ls17 ws2">SST39LF/VF160</div><div class="t m0 x9 h2 y20 ff3 fs0 fc0 sc0 ls18 ws17">•<span class="_ _7"> </span>A<span class="_ _1"></span>utomatic Write Timing</div><div class="t m0 xa h6 y21 ff2 fs0 fc0 sc0 ls9 ws7">–<span class="_ _8"> </span>Inter<span class="_ _0"></span>nal V</div><div class="t m0 xb h7 y22 ff2 fs4 fc0 sc0 ls19 ws2">PP</div><div class="t m0 xc h6 y23 ff2 fs0 fc0 sc0 ls13 ws16"> Generatio<span class="_ _0"></span>n</div><div class="t m0 x9 h2 y24 ff3 fs0 fc0 sc0 ls1a ws18">•<span class="_ _7"> </span>End-of-Wri<span class="_ _1"></span>te Detection</div><div class="t m0 xa h6 y25 ff2 fs0 fc0 sc0 ls1b ws19">–<span class="_ _8"> </span>T<span class="_ _4"></span>oggle Bit</div><div class="t m0 xa h6 y26 ff2 fs0 fc0 sc0 ls1c ws1a">–<span class="_ _8"> </span>Data# Polling</div><div class="t m0 x9 h2 y27 ff3 fs0 fc0 sc0 lsc wsa">•<span class="_ _7"> </span>CMOS I<span class="_ _0"></span>/O Compatibility </div><div class="t m0 x9 h2 y28 ff3 fs0 fc0 sc0 ls1d ws1b">•<span class="_ _7"> </span>JEDEC Sta<span class="_ _1"></span>ndard</div><div class="t m0 xa h6 y29 ff2 fs0 fc0 sc0 ls1e ws1c">–<span class="_ _8"> </span>Flash <span class="_ _0"></span>EEPROM Pino<span class="_ _0"></span>uts and c<span class="_ _0"></span>ommand s<span class="_ _0"></span>ets</div><div class="t m0 x9 h2 y2a ff3 fs0 fc0 sc0 ls1f ws1d">•<span class="_ _7"> </span>P<span class="_ _1"></span>ac<span class="_ _5"></span>kages A<span class="_ _5"></span>va<span class="_ _1"></span>ilab<span class="_ _1"></span>le</div><div class="t m0 xa h6 y2b ff2 fs0 fc0 sc0 ls10 ws14">–<span class="_ _8"> </span>48-lead<span class="_ _0"></span> TSOP (12mm<span class="_ _0"></span> x 20mm)</div><div class="t m0 xa h6 y2c ff2 fs0 fc0 sc0 ls20 ws1e">–<span class="_ _8"> </span>48-ball<span class="_ _0"></span> TFBGA<span class="_ _0"></span> (6mm x 8<span class="_ _0"></span>mm)</div><div class="t m0 x2 h5 y2d ff3 fs3 fc0 sc0 ls21 ws1f">PRODUCT DESCRIPTION</div><div class="t m0 x2 h6 y2e ff2 fs0 fc0 sc0 ls22 ws20">The SS<span class="_ _0"></span>T39L<span class="_ _0"></span>F/VF16<span class="_ _0"></span>0 devices <span class="_ _0"></span>are 1M x<span class="_ _0"></span>16 CMOS<span class="_ _0"></span> Mult<span class="_ _0"></span>i-</div><div class="t m0 x2 h6 y2f ff2 fs0 fc0 sc0 ls23 ws21">Pur<span class="_ _0"></span>p<span class="_ _0"></span>ose Flash (MP<span class="_ _0"></span>F) manufactured<span class="_ _0"></span> with SST’<span class="_ _1"></span>s propr<span class="_ _0"></span>ietar<span class="_ _0"></span>y<span class="_ _5"></span>,</div><div class="t m0 x2 h6 y30 ff2 fs0 fc0 sc0 ls24 ws22">high pe<span class="_ _0"></span>rf<span class="_ _1"></span>or<span class="_ _0"></span>man<span class="_ _0"></span>ce CMO<span class="_ _0"></span>S Supe<span class="_ _0"></span>rFlash <span class="_ _0"></span>technol<span class="_ _0"></span>og<span class="_ _1"></span>y<span class="_ _4"></span>. T<span class="_ _0"></span>he</div><div class="t m0 x2 h6 y31 ff2 fs0 fc0 sc0 ls25 ws23">split-<span class="_ _0"></span>gate<span class="_ _0"></span> cell <span class="_ _0"></span>design<span class="_ _0"></span> and<span class="_ _0"></span> thick <span class="_ _0"></span>oxide tunn<span class="_ _0"></span>elin<span class="_ _0"></span>g inje<span class="_ _0"></span>ctor</div><div class="t m0 x2 h6 y32 ff2 fs0 fc0 sc0 ls26 ws24">attain be<span class="_ _0"></span>tter rel<span class="_ _0"></span>iability<span class="_ _0"></span> and manufacturabili<span class="_ _0"></span>ty comp<span class="_ _0"></span>ared wit<span class="_ _0"></span>h</div><div class="t m0 x2 h6 y33 ff2 fs0 fc0 sc0 ls24 ws25">alter<span class="_ _0"></span>nate<span class="_ _0"></span> approac<span class="_ _0"></span>hes. The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>160 wr<span class="_ _0"></span>ite (Pr<span class="_ _0"></span>ogram or</div><div class="t m0 x2 h6 y34 ff2 fs0 fc0 sc0 ls27 ws26">Erase) wit<span class="_ _0"></span>h a 3.0-<span class="_ _0"></span>3.6V power su<span class="_ _0"></span>pply<span class="_ _4"></span>.<span class="_ _0"></span> The SST3<span class="_ _0"></span>9VF16<span class="_ _0"></span>0</div><div class="t m0 x2 h6 y35 ff2 fs0 fc0 sc0 ls24 ws27">wri<span class="_ _0"></span>te (Program or<span class="_ _0"></span> Erase) with<span class="_ _0"></span> a 2.7-3.<span class="_ _0"></span>6V power supply<span class="_ _5"></span>.</div><div class="t m0 x2 h6 y36 ff2 fs0 fc0 sc0 ls24 ws0">These devices c<span class="_ _0"></span>onform <span class="_ _0"></span>to JEDE<span class="_ _0"></span>C standa<span class="_ _0"></span>rd pino<span class="_ _0"></span>uts for x16</div><div class="t m0 x2 h6 y37 ff2 fs0 fc0 sc0 ls24 ws2">memor<span class="_ _0"></span>ies.</div><div class="t m0 x2 h6 y38 ff2 fs0 fc0 sc0 ls0 ws28">F<span class="_ _1"></span>eatur<span class="_ _0"></span>ing hig<span class="_ _0"></span>h performanc<span class="_ _0"></span>e Word-Program, the</div><div class="t m0 x2 h6 y39 ff2 fs0 fc0 sc0 ls28 ws29">SST39L<span class="_ _0"></span>F/VF16<span class="_ _0"></span>0 de<span class="_ _1"></span>vices<span class="_ _0"></span> provide a typ<span class="_ _0"></span>ical Word-Pro-</div><div class="t m0 x2 h6 y3a ff2 fs0 fc0 sc0 ls0 ws0">gram time of 1<span class="_ _0"></span>4 µsec. Th<span class="_ _0"></span>ese devices use T<span class="_ _4"></span>oggle B<span class="_ _0"></span>it or</div><div class="t m0 x2 h6 y3b ff2 fs0 fc0 sc0 ls13 ws2a">Data# P<span class="_ _1"></span>olling to indi<span class="_ _0"></span>cate the comp<span class="_ _0"></span>letion<span class="_ _0"></span> of Program</div><div class="t m0 x2 h6 y3c ff2 fs0 fc0 sc0 ls9 ws2b">operation. T<span class="_ _4"></span>o protec<span class="_ _0"></span>t agains<span class="_ _0"></span>t inadver<span class="_ _0"></span>tent wr<span class="_ _0"></span>ite, they</div><div class="t m0 x2 h6 y3d ff2 fs0 fc0 sc0 ls9 ws2c">hav<span class="_ _1"></span>e on-chip ha<span class="_ _0"></span>rdware and S<span class="_ _0"></span>oftware Data P<span class="_ _0"></span>rotectio<span class="_ _0"></span>n</div><div class="t m0 x2 h6 y3e ff2 fs0 fc0 sc0 lsb ws2d">schemes. Des<span class="_ _0"></span>igned, ma<span class="_ _0"></span>nuf<span class="_ _1"></span>acture<span class="_ _0"></span>d, and teste<span class="_ _0"></span>d for a</div><div class="t m0 x2 h6 y3f ff2 fs0 fc0 sc0 ls11 ws2e">wide spe<span class="_ _0"></span>ctru<span class="_ _0"></span>m of a<span class="_ _0"></span>pplic<span class="_ _0"></span>ations, thes<span class="_ _0"></span>e devices ar<span class="_ _0"></span>e</div><div class="t m0 x2 h6 y40 ff2 fs0 fc0 sc0 ls13 ws16">offered with a guaranteed en<span class="_ _0"></span>durance of 10,00<span class="_ _0"></span>0 cycles.</div><div class="t m0 x2 h6 y41 ff2 fs0 fc0 sc0 ls0 ws0">Data reten<span class="_ _0"></span>tion is rated <span class="_ _0"></span>at greater th<span class="_ _0"></span>an 100 years.</div><div class="t m0 x2 h6 y42 ff2 fs0 fc0 sc0 ls29 ws2f">The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>/VF16<span class="_ _0"></span>0 devices ar<span class="_ _0"></span>e suit<span class="_ _0"></span>ed for applic<span class="_ _0"></span>atio<span class="_ _0"></span>ns</div><div class="t m0 x2 h6 y43 ff2 fs0 fc0 sc0 ls2a ws30">that req<span class="_ _0"></span>uire convenient an<span class="_ _0"></span>d econo<span class="_ _0"></span>mical upd<span class="_ _0"></span>ating of <span class="_ _0"></span>pro-</div><div class="t m0 x2 h6 y44 ff2 fs0 fc0 sc0 ls2b ws31">gr<span class="_ _1"></span>am,<span class="_ _1"></span> configur<span class="_ _1"></span>at<span class="_ _1"></span>ion, or<span class="_ _1"></span> data me<span class="_ _1"></span>mory<span class="_ _4"></span>. Fo<span class="_ _1"></span>r all syst<span class="_ _1"></span>em app<span class="_ _1"></span>li-</div><div class="t m0 x2 h6 y45 ff2 fs0 fc0 sc0 ls2c ws32">cations, th<span class="_ _0"></span>ey signif<span class="_ _0"></span>icantly<span class="_ _0"></span> improve performa<span class="_ _0"></span>nce an<span class="_ _0"></span>d</div><div class="t m0 x2 h6 y46 ff2 fs0 fc0 sc0 ls2c ws33">relia<span class="_ _0"></span>bility<span class="_ _5"></span>, whi<span class="_ _0"></span>le loweri<span class="_ _0"></span>ng power cons<span class="_ _0"></span>umpti<span class="_ _0"></span>on. They in<span class="_ _0"></span>her-</div><div class="t m0 x2 h6 y47 ff2 fs0 fc0 sc0 ls2d ws1d">ently <span class="_ _0"></span>use les<span class="_ _0"></span>s energy dur<span class="_ _0"></span>ing<span class="_ _0"></span> Erase and<span class="_ _0"></span> Program <span class="_ _0"></span>than al<span class="_ _0"></span>ter-</div><div class="t m0 x2 h6 y48 ff2 fs0 fc0 sc0 ls2e ws34">native flash te<span class="_ _0"></span>chnolo<span class="_ _0"></span>gies. The to<span class="_ _0"></span>tal energy consu<span class="_ _0"></span>med is a</div><div class="t m0 x2 h6 y49 ff2 fs0 fc0 sc0 ls2e ws9">functio<span class="_ _0"></span>n of th<span class="_ _0"></span>e appli<span class="_ _0"></span>ed voltage, cur<span class="_ _0"></span>rent, an<span class="_ _0"></span>d time of<span class="_ _0"></span> applic<span class="_ _0"></span>a-</div><div class="t m0 x9 h6 y4a ff2 fs0 fc0 sc0 ls2e ws35">tion. Si<span class="_ _0"></span>nce for any given voltage range, the S<span class="_ _0"></span>uperF<span class="_ _0"></span>lash</div><div class="t m0 x9 h6 y4b ff2 fs0 fc0 sc0 ls2e ws36">technol<span class="_ _0"></span>ogy uses less cur<span class="_ _0"></span>rent to p<span class="_ _0"></span>rogram and h<span class="_ _0"></span>as a shor<span class="_ _9"></span>ter</div><div class="t m0 x9 h6 y4c ff2 fs0 fc0 sc0 ls2d wse">erase time, the tot<span class="_ _0"></span>al ene<span class="_ _0"></span>rg<span class="_ _1"></span>y consu<span class="_ _0"></span>med dur<span class="_ _0"></span>ing<span class="_ _0"></span> any Erase or</div><div class="t m0 x9 h6 y4d ff2 fs0 fc0 sc0 ls2f ws37">Program o<span class="_ _0"></span>peration is<span class="_ _0"></span> less<span class="_ _0"></span> than al<span class="_ _0"></span>ter<span class="_ _0"></span>native flash <span class="_ _0"></span>techn<span class="_ _0"></span>olo-</div><div class="t m0 x9 h6 y4e ff2 fs0 fc0 sc0 ls30 ws29">gies. These<span class="_ _0"></span> devices also<span class="_ _0"></span> improve flexibility wh<span class="_ _0"></span>ile lower<span class="_ _0"></span>ing</div><div class="t m0 x9 h6 y4f ff2 fs0 fc0 sc0 ls23 ws38">the cos<span class="_ _0"></span>t for program, data<span class="_ _0"></span>, and con<span class="_ _0"></span>figurat<span class="_ _0"></span>ion sto<span class="_ _0"></span>rage appl<span class="_ _0"></span>i-</div><div class="t m0 x9 h6 y50 ff2 fs0 fc0 sc0 ls31 ws2">cations.</div><div class="t m0 x9 h6 y51 ff2 fs0 fc0 sc0 ls27 ws39">The S<span class="_ _0"></span>uperFlas<span class="_ _0"></span>h te<span class="_ _0"></span>chnology pr<span class="_ _0"></span>ovides fi<span class="_ _0"></span>x<span class="_ _1"></span>ed Eras<span class="_ _0"></span>e and P<span class="_ _0"></span>ro-</div><div class="t m0 x9 h6 y52 ff2 fs0 fc0 sc0 ls2e ws3a">gram times, in<span class="_ _0"></span>depende<span class="_ _0"></span>nt of th<span class="_ _0"></span>e numbe<span class="_ _0"></span>r of Erase/<span class="_ _0"></span>Program</div><div class="t m0 x9 h6 y53 ff2 fs0 fc0 sc0 ls27 ws3b">cycl<span class="_ _0"></span>es that h<span class="_ _0"></span>av<span class="_ _1"></span>e occu<span class="_ _0"></span>rred. T<span class="_ _0"></span>herefore the s<span class="_ _0"></span>ystem<span class="_ _0"></span> software</div><div class="t m0 x9 h6 y54 ff2 fs0 fc0 sc0 ls26 ws12">or hardwa<span class="_ _0"></span>re doe<span class="_ _0"></span>s not h<span class="_ _0"></span>av<span class="_ _1"></span>e to be<span class="_ _0"></span> modifi<span class="_ _0"></span>ed or <span class="_ _0"></span>de-rated<span class="_ _0"></span> as is</div><div class="t m0 x9 h6 y55 ff2 fs0 fc0 sc0 ls32 ws3c">nece<span class="_ _0"></span>ssar<span class="_ _0"></span>y<span class="_ _0"></span> with a<span class="_ _0"></span>lter<span class="_ _0"></span>nat<span class="_ _0"></span>ive flash te<span class="_ _0"></span>chnolog<span class="_ _0"></span>ies, who<span class="_ _0"></span>se Eras<span class="_ _0"></span>e</div><div class="t m0 x9 h6 y56 ff2 fs0 fc0 sc0 ls33 ws3d">and Pr<span class="_ _0"></span>ogram times<span class="_ _0"></span> increas<span class="_ _0"></span>e with<span class="_ _0"></span> accumul<span class="_ _0"></span>ated E<span class="_ _0"></span>rase/Pro-</div><div class="t m0 x9 h6 y57 ff2 fs0 fc0 sc0 ls2b ws3e">gr<span class="_ _1"></span>am cycl<span class="_ _1"></span>es.</div><div class="t m0 x9 h6 y58 ff2 fs0 fc0 sc0 ls2f ws3f">T<span class="_ _4"></span>o meet high de<span class="_ _0"></span>nsit<span class="_ _0"></span>y<span class="_ _4"></span>, surface mou<span class="_ _0"></span>nt requi<span class="_ _0"></span>rements, th<span class="_ _0"></span>e</div><div class="t m0 x9 h6 y59 ff2 fs0 fc0 sc0 ls27 ws40">SST39<span class="_ _0"></span>LF/VF16<span class="_ _0"></span>0 are offered in 48-<span class="_ _0"></span>lead TS<span class="_ _0"></span>OP and 48-b<span class="_ _0"></span>all</div><div class="t m0 x9 h6 y5a ff2 fs0 fc0 sc0 ls2f ws9">TFBGA<span class="_ _0"></span> packages. See F<span class="_ _0"></span>igure 1<span class="_ _0"></span> for pinout<span class="_ _0"></span>s.</div><div class="t m0 x9 h5 y5b ff3 fs3 fc0 sc0 ls34 ws41">Device Operation</div><div class="t m0 x9 h6 y5c ff2 fs0 fc0 sc0 ls2e ws42">Comma<span class="_ _0"></span>nds are us<span class="_ _0"></span>ed to<span class="_ _0"></span> initiat<span class="_ _0"></span>e the m<span class="_ _0"></span>emor<span class="_ _0"></span>y o<span class="_ _0"></span>peration f<span class="_ _0"></span>unc-</div><div class="t m0 x9 h6 y5d ff2 fs0 fc0 sc0 ls2e ws43">tions of<span class="_ _0"></span> the device. Comman<span class="_ _0"></span>ds are w<span class="_ _0"></span>rit<span class="_ _0"></span>ten to th<span class="_ _0"></span>e device</div><div class="t m0 x9 h6 y5e ff2 fs0 fc0 sc0 ls32 ws44">using s<span class="_ _0"></span>tanda<span class="_ _0"></span>rd micr<span class="_ _0"></span>oproc<span class="_ _0"></span>essor wr<span class="_ _0"></span>it<span class="_ _0"></span>e sequen<span class="_ _0"></span>ces. A co<span class="_ _0"></span>m-</div><div class="t m0 x9 h6 y5f ff2 fs0 fc0 sc0 ls33 ws45">mand is<span class="_ _0"></span> written<span class="_ _0"></span> by asser<span class="_ _9"></span>ting WE<span class="_ _0"></span># low while keeping<span class="_ _0"></span> CE#</div><div class="t m0 x9 h6 y60 ff2 fs0 fc0 sc0 ls23 ws46">low<span class="_ _5"></span>. T<span class="_ _0"></span>he add<span class="_ _0"></span>ress <span class="_ _0"></span>bus is la<span class="_ _0"></span>tched o<span class="_ _0"></span>n the<span class="_ _0"></span> falling edge<span class="_ _0"></span> of WE<span class="_ _0"></span>#</div><div class="t m0 x9 h6 y61 ff2 fs0 fc0 sc0 ls26 ws47">or CE#, <span class="_ _0"></span>whichev<span class="_ _1"></span>er occu<span class="_ _0"></span>rs last.<span class="_ _0"></span> The data<span class="_ _0"></span> bus is latc<span class="_ _0"></span>hed on</div><div class="t m0 x9 h6 y62 ff2 fs0 fc0 sc0 ls24 ws14">the r<span class="_ _0"></span>ising<span class="_ _0"></span> edge of <span class="_ _0"></span>WE# <span class="_ _0"></span>or CE#,<span class="_ _0"></span> whichev<span class="_ _1"></span>er occ<span class="_ _0"></span>urs firs<span class="_ _0"></span>t.</div><div class="t m0 xd h3 y63 ff2 fs1 fc1 sc0 ls35 ws48">SST39LF/<span class="_ _1"></span>VF1603<span class="_ _1"></span>.0 & 2.7V 16<span class="_ _1"></span>Mb (x16) MP<span class="_ _1"></span>F memories</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/bg2.jpg"><div class="t m2 xe h8 y64 ff2 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m2 x2 h6 y1 ff2 fs0 fc0 sc0 ls14 ws49">Data Sheet</div><div class="t m2 xf h9 y65 ff3 fs6 fc0 sc0 ls36 ws4a">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m2 x10 h9 y66 ff3 fs6 fc0 sc0 ls37 ws2">SST39LF160 / SST39VF1<span class="_ _0"></span>60</div><div class="t m2 x2 h3 y2 ff2 fs1 fc0 sc0 ls38 ws4b">©<span class="_ _0"></span>2002 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>2/02<span class="_ _a"> </span>399</span></div><div class="t m2 x2 h6 y67 ff2 fs0 fc0 sc0 ls23 ws4c">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 al<span class="_ _0"></span>so hav<span class="_ _1"></span>e the<span class="_ _0"></span> <span class="ff3 ls39 ws4d">A<span class="_ _1"></span>uto Low P<span class="_ _5"></span>ower</span></div><div class="t m2 x2 h6 y68 ff2 fs0 fc0 sc0 ls2f ws4e">mode whic<span class="_ _0"></span>h puts the device<span class="_ _0"></span> in a near stand<span class="_ _0"></span>by mode after</div><div class="t m2 x2 h6 y69 ff2 fs0 fc0 sc0 ls3a ws4f">data<span class="_ _1"></span> has be<span class="_ _1"></span>en acce<span class="_ _1"></span>ssed w<span class="_ _1"></span>ith a <span class="_ _1"></span>va<span class="_ _1"></span>lid Re<span class="_ _1"></span>ad ope<span class="_ _1"></span>rati<span class="_ _1"></span>on. T<span class="_ _1"></span>his</div><div class="t m2 x2 h6 y6a ff2 fs0 fc0 sc0 ls3b ws50">reduce<span class="_ _0"></span>s the <span class="_ _0"></span>I</div><div class="t m2 x11 h7 y6b ff2 fs4 fc0 sc0 ls3c ws2">DD</div><div class="t m2 x12 h6 y6c ff2 fs0 fc0 sc0 ls33 ws51"> active read current fr<span class="_ _0"></span>om typical<span class="_ _0"></span>ly 15 mA to</div><div class="t m2 x2 h6 y6d ff2 fs0 fc0 sc0 ls27 ws52">typica<span class="_ _0"></span>lly 4 µA<span class="_ _0"></span>. The Auto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er mode<span class="_ _0"></span> reduce<span class="_ _0"></span>s the ty<span class="_ _0"></span>pi-</div><div class="t m2 x2 h6 y6e ff2 fs0 fc0 sc0 ls3d ws53">cal I</div><div class="t m2 x13 h7 y6f ff2 fs4 fc0 sc0 ls3c ws2">DD</div><div class="t m2 x14 h6 y70 ff2 fs0 fc0 sc0 ls33 ws54"> active read cur<span class="_ _0"></span>rent to t<span class="_ _0"></span>he range o<span class="_ _0"></span>f 1 mA/MHz<span class="_ _0"></span> of</div><div class="t m2 x2 h6 y71 ff2 fs0 fc0 sc0 ls3e ws55">read cyc<span class="_ _1"></span>le time<span class="_ _1"></span>. The de<span class="_ _1"></span>vice<span class="_ _1"></span> e<span class="_ _1"></span>xits the A<span class="_ _1"></span>uto<span class="_ _1"></span> Low P<span class="_ _5"></span>owe<span class="_ _1"></span>r</div><div class="t m2 x2 h6 y72 ff2 fs0 fc0 sc0 ls3f ws56">mode wit<span class="_ _0"></span>h any add<span class="_ _0"></span>ress <span class="_ _0"></span>transition<span class="_ _0"></span> or con<span class="_ _0"></span>trol s<span class="_ _0"></span>ignal tra<span class="_ _0"></span>nsition</div><div class="t m2 x2 h6 y73 ff2 fs0 fc0 sc0 ls3f ws57">used to i<span class="_ _0"></span>nitiate a<span class="_ _0"></span>nothe<span class="_ _0"></span>r Read<span class="_ _0"></span> cycle, with no<span class="_ _0"></span> acces<span class="_ _0"></span>s time</div><div class="t m2 x2 h6 y74 ff2 fs0 fc0 sc0 ls40 ws58">penalty<span class="_ _5"></span>. Note th<span class="_ _0"></span>at the<span class="_ _0"></span> de<span class="_ _1"></span>vice d<span class="_ _0"></span>oes not<span class="_ _0"></span> enter Auto Low</div><div class="t m2 x2 h6 y75 ff2 fs0 fc0 sc0 ls41 ws59">P<span class="_ _5"></span>owe<span class="_ _1"></span>r mode<span class="_ _1"></span> afte<span class="_ _1"></span>r po<span class="_ _1"></span>w<span class="_ _1"></span>er-up<span class="_ _1"></span> wi<span class="_ _1"></span>th CE<span class="_ _1"></span># held<span class="_ _1"></span> stea<span class="_ _1"></span>dily <span class="_ _1"></span>low<span class="_ _1"></span> unti<span class="_ _1"></span>l</div><div class="t m2 x2 h6 y76 ff2 fs0 fc0 sc0 ls42 ws3c">the f<span class="_ _1"></span>irst a<span class="_ _1"></span>ddre<span class="_ _1"></span>ss tran<span class="_ _1"></span>siti<span class="_ _1"></span>on or<span class="_ _1"></span> CE# is driv<span class="_ _5"></span>en high.</div><div class="t m2 x2 h5 y77 ff3 fs3 fc0 sc0 ls43 ws2">Read</div><div class="t m2 x2 h6 y78 ff2 fs0 fc0 sc0 ls23 ws5a">The Read operation of <span class="_ _1"></span>the SST39LF/VF160 is controlled by</div><div class="t m2 x2 h6 y79 ff2 fs0 fc0 sc0 ls2f ws36">CE# and OE#, both ha<span class="_ _1"></span>v<span class="_ _1"></span>e to be low f<span class="_ _1"></span>or the system to obtain</div><div class="t m2 x2 h6 y7a ff2 fs0 fc0 sc0 ls27 ws26">data from the outputs. CE# is used for de<span class="_ _1"></span>vice selection.</div><div class="t m2 x2 h6 y7b ff2 fs0 fc0 sc0 ls30 ws5b">When CE# is high, the chip <span class="_ _0"></span>is deselected and only s<span class="_ _0"></span>tandby</div><div class="t m2 x2 h6 y7c ff2 fs0 fc0 sc0 ls27 ws40">pow<span class="_ _1"></span>er is consumed. OE# is the output control and <span class="_ _1"></span>is used</div><div class="t m2 x2 h6 y7d ff2 fs0 fc0 sc0 ls26 ws5c">to gate data from the output pins. The data b<span class="_ _1"></span>us is in high</div><div class="t m2 x2 h6 y7e ff2 fs0 fc0 sc0 ls2e ws5d">impedance state when either CE# or<span class="_ _0"></span> OE# is high. Ref<span class="_ _1"></span>er to</div><div class="t m2 x2 h6 y7f ff2 fs0 fc0 sc0 ls30 ws5e">the Read cycle timing diagram <span class="_ _1"></span>for<span class="_ _1"></span> fur<span class="_ _0"></span>ther details (Figure 2).</div><div class="t m2 x2 h5 y80 ff3 fs3 fc0 sc0 ls44 ws5f">Word-Program<span class="_ _1"></span> Operation</div><div class="t m2 x2 h6 y81 ff2 fs0 fc0 sc0 ls2e ws60">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 <span class="_ _0"></span>are pr<span class="_ _0"></span>ogrammed on<span class="_ _0"></span> a word-<span class="_ _0"></span>by-word</div><div class="t m2 x2 h6 y82 ff2 fs0 fc0 sc0 ls45 ws61">bas<span class="_ _1"></span>is. B<span class="_ _1"></span>ef<span class="_ _1"></span>ore<span class="_ _1"></span> prog<span class="_ _1"></span>r<span class="_ _1"></span>ammi<span class="_ _1"></span>ng, th<span class="_ _1"></span>e secto<span class="_ _1"></span>r wher<span class="_ _1"></span>e the w<span class="_ _1"></span>ord</div><div class="t m2 x2 h6 y83 ff2 fs0 fc0 sc0 ls3b ws62">ex<span class="_ _1"></span>ists<span class="_ _0"></span> must be fully era<span class="_ _0"></span>sed. The<span class="_ _0"></span> Program operatio<span class="_ _0"></span>n is</div><div class="t m2 x2 h6 y84 ff2 fs0 fc0 sc0 ls2d ws49">accomp<span class="_ _0"></span>lishe<span class="_ _0"></span>d in three<span class="_ _0"></span> step<span class="_ _0"></span>s. The first <span class="_ _0"></span>step is<span class="_ _0"></span> the thr<span class="_ _0"></span>ee-byte</div><div class="t m2 x2 h6 y85 ff2 fs0 fc0 sc0 ls2f ws37">load se<span class="_ _0"></span>quenc<span class="_ _0"></span>e f<span class="_ _1"></span>or So<span class="_ _0"></span>ftware Dat<span class="_ _0"></span>a Protecti<span class="_ _0"></span>on. The<span class="_ _0"></span> secon<span class="_ _0"></span>d</div><div class="t m2 x2 h6 y86 ff2 fs0 fc0 sc0 ls2f ws63">step<span class="_ _0"></span> is to load<span class="_ _0"></span> word a<span class="_ _0"></span>ddress a<span class="_ _0"></span>nd word<span class="_ _0"></span> data. Dur<span class="_ _0"></span>ing<span class="_ _0"></span> the</div><div class="t m2 x2 h6 y87 ff2 fs0 fc0 sc0 ls2f ws42">W<span class="_ _1"></span>ord-P<span class="_ _0"></span>rogram operat<span class="_ _0"></span>ion, t<span class="_ _0"></span>he addr<span class="_ _0"></span>esses ar<span class="_ _0"></span>e la<span class="_ _0"></span>tched on<span class="_ _0"></span> the</div><div class="t m2 x2 h6 y88 ff2 fs0 fc0 sc0 ls30 ws64">falling edge o<span class="_ _0"></span>f eit<span class="_ _0"></span>her CE#<span class="_ _0"></span> or WE<span class="_ _0"></span>#, whi<span class="_ _0"></span>chev<span class="_ _1"></span>er occ<span class="_ _0"></span>urs la<span class="_ _0"></span>st.</div><div class="t m2 x2 h6 y89 ff2 fs0 fc0 sc0 ls3f ws65">The dat<span class="_ _0"></span>a is la<span class="_ _0"></span>tched on<span class="_ _0"></span> the r<span class="_ _0"></span>isi<span class="_ _0"></span>ng edge <span class="_ _0"></span>of eit<span class="_ _0"></span>her CE#<span class="_ _0"></span> or</div><div class="t m2 x2 h6 y8a ff2 fs0 fc0 sc0 ls2d ws66">WE#, wh<span class="_ _0"></span>ichev<span class="_ _1"></span>er oc<span class="_ _0"></span>curs fi<span class="_ _0"></span>rst. The<span class="_ _0"></span> third<span class="_ _0"></span> step i<span class="_ _0"></span>s the i<span class="_ _0"></span>nter<span class="_ _0"></span>nal</div><div class="t m2 x2 h6 y8b ff2 fs0 fc0 sc0 ls2d wse">Program opera<span class="_ _0"></span>tion whi<span class="_ _0"></span>ch is i<span class="_ _0"></span>nitiate<span class="_ _0"></span>d after <span class="_ _0"></span>the r<span class="_ _0"></span>ising edg<span class="_ _0"></span>e of</div><div class="t m2 x2 h6 y8c ff2 fs0 fc0 sc0 ls41 ws67">the f<span class="_ _5"></span>our<span class="_ _0"></span>th WE# or<span class="_ _1"></span> CE#, wh<span class="_ _1"></span>iche<span class="_ _1"></span>v<span class="_ _5"></span>er occurs fir<span class="_ _1"></span>st. T<span class="_ _1"></span>he Pro-</div><div class="t m2 x2 h6 y8d ff2 fs0 fc0 sc0 ls46 ws68">gr<span class="_ _1"></span>am op<span class="_ _1"></span>erat<span class="_ _1"></span>ion, on<span class="_ _1"></span>ce init<span class="_ _1"></span>iated<span class="_ _1"></span>, will b<span class="_ _1"></span>e comple<span class="_ _1"></span>ted wi<span class="_ _1"></span>thin 20</div><div class="t m2 x2 h6 y8e ff2 fs0 fc0 sc0 ls46 ws69">µs<span class="_ _1"></span>. See Fi<span class="_ _1"></span>gure<span class="_ _1"></span>s 3 and 4 f<span class="_ _1"></span>o<span class="_ _1"></span>r WE# and<span class="_ _1"></span> CE# cont<span class="_ _1"></span>roll<span class="_ _1"></span>ed Pro<span class="_ _1"></span>-</div><div class="t m2 x2 h6 y8f ff2 fs0 fc0 sc0 ls47 ws6a">gr<span class="_ _1"></span>am op<span class="_ _1"></span>era<span class="_ _1"></span>tio<span class="_ _1"></span>n timi<span class="_ _1"></span>ng di<span class="_ _1"></span>agr<span class="_ _1"></span>ams an<span class="_ _1"></span>d Figu<span class="_ _1"></span>re 15 f<span class="_ _5"></span>or flo<span class="_ _1"></span>w-</div><div class="t m2 x2 h6 y90 ff2 fs0 fc0 sc0 ls23 ws6b">char<span class="_ _9"></span>ts. Dur<span class="_ _0"></span>ing the P<span class="_ _0"></span>rogram operatio<span class="_ _0"></span>n, the on<span class="_ _0"></span>ly valid reads</div><div class="t m2 x2 h6 y91 ff2 fs0 fc0 sc0 ls2d ws6c">are Data# P<span class="_ _1"></span>ollin<span class="_ _0"></span>g and T<span class="_ _4"></span>oggle Bit.<span class="_ _0"></span> Durin<span class="_ _0"></span>g the inter<span class="_ _0"></span>nal<span class="_ _0"></span> Pro-</div><div class="t m2 x2 h6 y92 ff2 fs0 fc0 sc0 ls48 ws1c">gr<span class="_ _1"></span>am op<span class="_ _1"></span>er<span class="_ _1"></span>ation<span class="_ _1"></span>, the <span class="_ _1"></span>host<span class="_ _1"></span> is fr<span class="_ _1"></span>ee to p<span class="_ _1"></span>erf<span class="_ _5"></span>or<span class="_ _0"></span>m addit<span class="_ _1"></span>ion<span class="_ _1"></span>al task<span class="_ _1"></span>s.</div><div class="t m2 x2 h6 y93 ff2 fs0 fc0 sc0 ls27 ws39">Any comman<span class="_ _0"></span>ds iss<span class="_ _0"></span>ued dur<span class="_ _0"></span>ing<span class="_ _0"></span> the inter<span class="_ _0"></span>nal<span class="_ _0"></span> Program ope<span class="_ _0"></span>ra-</div><div class="t m2 x2 h6 y94 ff2 fs0 fc0 sc0 ls2a ws6d">tion are ignor<span class="_ _0"></span>ed.</div><div class="t m2 x2 h5 y95 ff3 fs3 fc0 sc0 ls49 ws6e">Sector-/B<span class="_ _1"></span>lock-Erase Opera<span class="_ _1"></span>tion</div><div class="t m2 x2 h6 y96 ff2 fs0 fc0 sc0 ls4a ws6f">The <span class="_ _1"></span>Sector-<span class="_ _1"></span> (or Bl<span class="_ _1"></span>oc<span class="_ _1"></span>k-) Er<span class="_ _1"></span>ase<span class="_ _1"></span> oper<span class="_ _1"></span>ation<span class="_ _1"></span> allo<span class="_ _1"></span>ws th<span class="_ _1"></span>e syste<span class="_ _1"></span>m</div><div class="t m2 x2 h6 y97 ff2 fs0 fc0 sc0 ls2e ws70">to erase <span class="_ _0"></span>the device on a s<span class="_ _0"></span>ector<span class="_ _0"></span>-by-sector<span class="_ _0"></span> (or block-by-</div><div class="t m2 x2 h6 y98 ff2 fs0 fc0 sc0 ls2c ws71">block) basis. The<span class="_ _0"></span> SST3<span class="_ _0"></span>9LF/VF<span class="_ _0"></span>160 offer both<span class="_ _0"></span> Sec<span class="_ _0"></span>tor-Eras<span class="_ _0"></span>e</div><div class="t m2 x2 h6 y99 ff2 fs0 fc0 sc0 ls2d ws72">and Blo<span class="_ _0"></span>ck-Erase modes. T<span class="_ _0"></span>he sect<span class="_ _0"></span>or arc<span class="_ _0"></span>hitectu<span class="_ _0"></span>re is bas<span class="_ _0"></span>ed</div><div class="t m2 x2 h6 y9a ff2 fs0 fc0 sc0 ls2c ws71">on un<span class="_ _0"></span>if<span class="_ _1"></span>or<span class="_ _0"></span>m s<span class="_ _0"></span>ector<span class="_ _0"></span> size of <span class="_ _0"></span>2 KWord. Th<span class="_ _0"></span>e Bl<span class="_ _0"></span>ock-Erase m<span class="_ _0"></span>ode</div><div class="t m2 x9 h6 y9b ff2 fs0 fc0 sc0 ls32 ws73">is base<span class="_ _0"></span>d on uni<span class="_ _0"></span>f<span class="_ _1"></span>or<span class="_ _0"></span>m block size of 32 K<span class="_ _0"></span>Word. The Sec<span class="_ _0"></span>tor-</div><div class="t m2 x9 h6 y9c ff2 fs0 fc0 sc0 ls32 ws74">Erase ope<span class="_ _0"></span>ration is<span class="_ _0"></span> init<span class="_ _0"></span>iated<span class="_ _0"></span> b<span class="_ _1"></span>y ex<span class="_ _1"></span>ecuting<span class="_ _0"></span> a six-byte co<span class="_ _0"></span>m-</div><div class="t m2 x9 h6 y9d ff2 fs0 fc0 sc0 ls23 ws75">mand se<span class="_ _0"></span>quence wi<span class="_ _0"></span>th Se<span class="_ _0"></span>ctor-<span class="_ _0"></span>Erase comm<span class="_ _0"></span>and (<span class="_ _0"></span>30H) an<span class="_ _0"></span>d</div><div class="t m2 x9 h6 y9e ff2 fs0 fc0 sc0 ls4b ws76">secto<span class="_ _1"></span>r addres<span class="_ _1"></span>s (SA) in th<span class="_ _1"></span>e last b<span class="_ _1"></span>us cycle<span class="_ _1"></span>. The Blo<span class="_ _1"></span>c<span class="_ _1"></span>k-Erase</div><div class="t m2 x9 h6 y9f ff2 fs0 fc0 sc0 ls30 ws77">operatio<span class="_ _0"></span>n is ini<span class="_ _0"></span>tiate<span class="_ _0"></span>d by e<span class="_ _1"></span>x<span class="_ _1"></span>ecut<span class="_ _0"></span>ing a si<span class="_ _0"></span>x-byte co<span class="_ _0"></span>mman<span class="_ _0"></span>d</div><div class="t m2 x9 h6 ya0 ff2 fs0 fc0 sc0 ls2f ws78">sequenc<span class="_ _0"></span>e with <span class="_ _0"></span>Block-Eras<span class="_ _0"></span>e comma<span class="_ _0"></span>nd (50<span class="_ _0"></span>H) and block</div><div class="t m2 x9 h6 ya1 ff2 fs0 fc0 sc0 ls4c ws79">address <span class="_ _1"></span>(BA) in<span class="_ _1"></span> the last b<span class="_ _1"></span>us c<span class="_ _1"></span>ycle<span class="_ _1"></span>. The sect<span class="_ _1"></span>or or <span class="_ _1"></span>bloc<span class="_ _1"></span>k</div><div class="t m2 x9 h6 ya2 ff2 fs0 fc0 sc0 ls3f ws7a">addres<span class="_ _0"></span>s is latc<span class="_ _0"></span>hed o<span class="_ _0"></span>n the falling ed<span class="_ _0"></span>ge of the s<span class="_ _0"></span>ixt<span class="_ _0"></span>h WE#</div><div class="t m2 x9 h6 ya3 ff2 fs0 fc0 sc0 ls23 ws7b">pulse, whil<span class="_ _0"></span>e the co<span class="_ _0"></span>mmand (3<span class="_ _0"></span>0H or 50H)<span class="_ _0"></span> is latc<span class="_ _0"></span>hed on the</div><div class="t m2 x9 h6 ya4 ff2 fs0 fc0 sc0 ls3b ws7c">risi<span class="_ _0"></span>ng edg<span class="_ _0"></span>e of th<span class="_ _0"></span>e sixt<span class="_ _0"></span>h WE# p<span class="_ _0"></span>ulse. The<span class="_ _0"></span> inter<span class="_ _0"></span>n<span class="_ _0"></span>al Erase</div><div class="t m2 x9 h6 ya5 ff2 fs0 fc0 sc0 ls3f ws7d">operatio<span class="_ _0"></span>n begins<span class="_ _0"></span> after <span class="_ _0"></span>the si<span class="_ _0"></span>xth WE<span class="_ _0"></span># puls<span class="_ _0"></span>e. The End<span class="_ _0"></span>-of-</div><div class="t m2 x9 h6 ya6 ff2 fs0 fc0 sc0 ls23 ws7e">Erase op<span class="_ _0"></span>eration c<span class="_ _0"></span>an be deter<span class="_ _0"></span>m<span class="_ _0"></span>ined u<span class="_ _0"></span>sing ei<span class="_ _0"></span>ther Data<span class="_ _0"></span>#</div><div class="t m2 x9 h6 ya7 ff2 fs0 fc0 sc0 ls23 ws7f">P<span class="_ _1"></span>olling or T<span class="_ _4"></span>oggle Bi<span class="_ _0"></span>t method<span class="_ _0"></span>s. See Figures<span class="_ _0"></span> 8 and 9 f<span class="_ _1"></span>or tim-</div><div class="t m2 x9 h6 ya8 ff2 fs0 fc0 sc0 ls23 ws3b">ing wavef<span class="_ _1"></span>orms. A<span class="_ _0"></span>ny comman<span class="_ _0"></span>ds issue<span class="_ _0"></span>d dur<span class="_ _0"></span>ing<span class="_ _0"></span> the S<span class="_ _0"></span>ector-</div><div class="t m2 x9 h6 ya9 ff2 fs0 fc0 sc0 ls2e ws16">or Blo<span class="_ _0"></span>ck-Erase operat<span class="_ _0"></span>ion are<span class="_ _0"></span> ignor<span class="_ _0"></span>ed.</div><div class="t m2 x9 h5 yaa ff3 fs3 fc0 sc0 ls4d ws80">Chip-Erase Oper<span class="_ _1"></span>ation</div><div class="t m2 x9 h6 yab ff2 fs0 fc0 sc0 ls3f ws81">The SST39LF/VF160 provide a <span class="_ _1"></span>Chip-Erase operation,</div><div class="t m2 x9 h6 yac ff2 fs0 fc0 sc0 ls23 ws82">which allows the user<span class="_ _1"></span> to erase th<span class="_ _1"></span>e entire memor<span class="_ _0"></span>y arra<span class="_ _1"></span>y to</div><div class="t m2 x9 h6 yad ff2 fs0 fc0 sc0 ls30 ws83">the “1” state. This is useful <span class="_ _0"></span>when the entire device must be</div><div class="t m2 x9 h6 yae ff2 fs0 fc0 sc0 ls32 ws84">quickly erased.</div><div class="t m2 x9 h6 yaf ff2 fs0 fc0 sc0 ls32 ws85">The Ch<span class="_ _0"></span>ip-Era<span class="_ _0"></span>se o<span class="_ _0"></span>peration <span class="_ _0"></span>is in<span class="_ _0"></span>itia<span class="_ _0"></span>ted by ex<span class="_ _1"></span>ecuti<span class="_ _0"></span>ng a s<span class="_ _0"></span>ix-</div><div class="t m2 x9 h6 yb0 ff2 fs0 fc0 sc0 ls2f ws86">byte comma<span class="_ _0"></span>nd seq<span class="_ _0"></span>uence w<span class="_ _0"></span>ith C<span class="_ _0"></span>hip-Eras<span class="_ _0"></span>e co<span class="_ _0"></span>mmand (<span class="_ _0"></span>10H)</div><div class="t m2 x9 h6 yb1 ff2 fs0 fc0 sc0 ls27 ws87">at addr<span class="_ _0"></span>ess 55<span class="_ _0"></span>55H in<span class="_ _0"></span> the las<span class="_ _0"></span>t byte se<span class="_ _0"></span>quence. Th<span class="_ _0"></span>e Erase</div><div class="t m2 x9 h6 yb2 ff2 fs0 fc0 sc0 ls2f ws88">operatio<span class="_ _0"></span>n begins wi<span class="_ _0"></span>th the ri<span class="_ _0"></span>sing edg<span class="_ _0"></span>e of the sixt<span class="_ _0"></span>h WE# or</div><div class="t m2 x9 h6 yb3 ff2 fs0 fc0 sc0 ls40 ws89">CE#, whic<span class="_ _0"></span>he<span class="_ _1"></span>ver occurs firs<span class="_ _0"></span>t. Dur<span class="_ _0"></span>ing the Era<span class="_ _0"></span>se operation<span class="_ _0"></span>,</div><div class="t m2 x9 h6 yb4 ff2 fs0 fc0 sc0 ls2f ws8a">the only<span class="_ _0"></span> v<span class="_ _1"></span>alid r<span class="_ _0"></span>ead is T<span class="_ _4"></span>oggl<span class="_ _0"></span>e Bit or<span class="_ _0"></span> Data# P<span class="_ _1"></span>olling.<span class="_ _0"></span> See T<span class="_ _4"></span>able</div><div class="t m2 x9 h6 yb5 ff2 fs0 fc0 sc0 ls24 ws8b">4 for the com<span class="_ _0"></span>mand s<span class="_ _0"></span>equence, Fi<span class="_ _0"></span>gure 7 <span class="_ _0"></span>f<span class="_ _1"></span>or ti<span class="_ _0"></span>ming di<span class="_ _0"></span>agram,</div><div class="t m2 x9 h6 yb6 ff2 fs0 fc0 sc0 ls23 ws8c">and Fi<span class="_ _0"></span>gure 1<span class="_ _0"></span>8 for the flowcha<span class="_ _0"></span>r<span class="_ _0"></span>t. <span class="_ _0"></span>Any comm<span class="_ _0"></span>ands<span class="_ _0"></span> issued <span class="_ _0"></span>dur-</div><div class="t m2 x9 h6 yb7 ff2 fs0 fc0 sc0 ls3f ws1c">ing t<span class="_ _0"></span>he Chip-E<span class="_ _0"></span>rase ope<span class="_ _0"></span>ration ar<span class="_ _0"></span>e ignor<span class="_ _0"></span>ed.</div><div class="t m2 x9 h5 yb8 ff3 fs3 fc0 sc0 ls4e ws8d">Write Opera<span class="_ _1"></span>tion Status Dete<span class="_ _1"></span>ction</div><div class="t m2 x9 h6 yb9 ff2 fs0 fc0 sc0 ls42 ws8e">The SST<span class="_ _1"></span>39LF/<span class="_ _1"></span>VF16<span class="_ _1"></span>0 prov<span class="_ _1"></span>ide tw<span class="_ _1"></span>o soft<span class="_ _1"></span>wa<span class="_ _1"></span>re means to</div><div class="t m2 x9 h6 yba ff2 fs0 fc0 sc0 ls2d ws8f">detect <span class="_ _0"></span>the com<span class="_ _0"></span>pletion<span class="_ _0"></span> of a <span class="_ _0"></span>Wr<span class="_ _0"></span>ite (P<span class="_ _0"></span>rogram or E<span class="_ _0"></span>rase) cyc<span class="_ _0"></span>le,</div><div class="t m2 x9 h6 ybb ff2 fs0 fc0 sc0 ls33 ws90">in order to op<span class="_ _0"></span>timize the sys<span class="_ _0"></span>tem Wr<span class="_ _0"></span>ite cycl<span class="_ _0"></span>e time. The soft-</div><div class="t m2 x9 h6 ybc ff2 fs0 fc0 sc0 ls2d ws91">ware detect<span class="_ _0"></span>ion inc<span class="_ _0"></span>ludes two s<span class="_ _0"></span>tatus bi<span class="_ _0"></span>ts: Data#<span class="_ _0"></span> P<span class="_ _1"></span>olling</div><div class="t m2 x9 h6 ybd ff2 fs0 fc0 sc0 ls4f ws2">(DQ</div><div class="t m2 x15 h7 ybe ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m2 x16 h6 ybf ff2 fs0 fc0 sc0 ls2d ws92">) and T<span class="_ _4"></span>oggl<span class="_ _0"></span>e Bit (D<span class="_ _0"></span>Q</div><div class="t m2 x17 h7 ybe ff2 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m2 x18 h6 ybf ff2 fs0 fc0 sc0 ls50 ws93">). The<span class="_ _0"></span> End-of-<span class="_ _0"></span>Wr<span class="_ _0"></span>ite dete<span class="_ _0"></span>ctio<span class="_ _0"></span>n</div><div class="t m2 x9 h6 yc0 ff2 fs0 fc0 sc0 ls23 ws94">mode is en<span class="_ _0"></span>abled after the<span class="_ _0"></span> ris<span class="_ _0"></span>ing edge of W<span class="_ _0"></span>E#, whic<span class="_ _0"></span>h ini-</div><div class="t m2 x9 h6 yc1 ff2 fs0 fc0 sc0 ls2d ws49">tiates <span class="_ _0"></span>the inter<span class="_ _0"></span>n<span class="_ _0"></span>al Pro<span class="_ _0"></span>gram or Erase o<span class="_ _0"></span>peration.</div><div class="t m2 x9 h6 yc2 ff2 fs0 fc0 sc0 ls27 ws95">The act<span class="_ _0"></span>ual comp<span class="_ _0"></span>leti<span class="_ _0"></span>on of the no<span class="_ _0"></span>nv<span class="_ _1"></span>olatile wr<span class="_ _0"></span>ite<span class="_ _0"></span> is asyn<span class="_ _0"></span>chro-</div><div class="t m2 x9 h6 yc3 ff2 fs0 fc0 sc0 ls33 ws96">nous wi<span class="_ _0"></span>th the sy<span class="_ _0"></span>stem; th<span class="_ _0"></span>erefore, either a D<span class="_ _0"></span>ata# P<span class="_ _1"></span>olling<span class="_ _0"></span> or</div><div class="t m2 x9 h6 yc4 ff2 fs0 fc0 sc0 ls2f ws97">T<span class="_ _4"></span>oggle B<span class="_ _0"></span>it read may be si<span class="_ _0"></span>multaneou<span class="_ _0"></span>s with th<span class="_ _0"></span>e compl<span class="_ _0"></span>etio<span class="_ _0"></span>n</div><div class="t m2 x9 h6 yc5 ff2 fs0 fc0 sc0 ls51 ws98">of the w<span class="_ _1"></span>rite cycle.<span class="_ _1"></span> If this o<span class="_ _1"></span>ccurs<span class="_ _1"></span>, the system m<span class="_ _1"></span>a<span class="_ _1"></span>y possib<span class="_ _1"></span>ly</div><div class="t m2 x9 h6 yc6 ff2 fs0 fc0 sc0 ls3b ws50">get a<span class="_ _0"></span>n erron<span class="_ _0"></span>eous <span class="_ _0"></span>resul<span class="_ _0"></span>t, i.e., valid<span class="_ _0"></span> data<span class="_ _0"></span> may appear<span class="_ _0"></span> to <span class="_ _0"></span>con-</div><div class="t m2 x9 h6 yc7 ff2 fs0 fc0 sc0 ls52 ws99">flict with e<span class="_ _0"></span>ither DQ</div><div class="t m2 xc h7 yc8 ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m2 x19 h6 yc9 ff2 fs0 fc0 sc0 ls53 ws9a"> or DQ</div><div class="t m2 x17 h7 yc8 ff2 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m2 x18 h6 yc9 ff2 fs0 fc0 sc0 ls2d ws9b">. In orde<span class="_ _0"></span>r to prev<span class="_ _1"></span>ent spur<span class="_ _0"></span>ious</div><div class="t m2 x9 h6 yca ff2 fs0 fc0 sc0 ls27 ws9c">rejec<span class="_ _0"></span>tion, i<span class="_ _0"></span>f an <span class="_ _0"></span>errone<span class="_ _0"></span>ous r<span class="_ _0"></span>esult o<span class="_ _0"></span>ccurs, the<span class="_ _0"></span> soft<span class="_ _0"></span>ware rout<span class="_ _0"></span>ine</div><div class="t m2 x9 h6 ycb ff2 fs0 fc0 sc0 ls22 ws9d">shou<span class="_ _0"></span>ld inc<span class="_ _0"></span>lude <span class="_ _0"></span>a loop to<span class="_ _0"></span> rea<span class="_ _0"></span>d the <span class="_ _0"></span>access<span class="_ _0"></span>ed l<span class="_ _0"></span>ocatio<span class="_ _0"></span>n an</div><div class="t m2 x9 h6 ycc ff2 fs0 fc0 sc0 ls2a ws9e">additio<span class="_ _0"></span>nal two (2) tim<span class="_ _0"></span>es. If both rea<span class="_ _0"></span>ds are valid, the<span class="_ _0"></span>n the</div><div class="t m2 x9 h6 ycd ff2 fs0 fc0 sc0 ls26 ws24">device has co<span class="_ _0"></span>mpleted <span class="_ _0"></span>the W<span class="_ _0"></span>rit<span class="_ _0"></span>e cycle, oth<span class="_ _0"></span>erwise<span class="_ _0"></span> the rejec<span class="_ _0"></span>-</div><div class="t m2 x9 h6 yce ff2 fs0 fc0 sc0 ls23 ws46">tion is valid.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/bg3.jpg"><div class="t m0 x1a h6 y1 ff2 fs0 fc0 sc0 ls54 ws2">Data Shee<span class="_ _0"></span>t</div><div class="t m0 x2 h9 y65 ff3 fs6 fc0 sc0 ls36 ws4a">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m0 x2 h9 y66 ff3 fs6 fc0 sc0 ls55 ws9f">SST39LF160 / SST39V<span class="_ _0"></span>F160</div><div class="t m0 xe h8 y64 ff2 fs5 fc0 sc0 ls3 ws2">3</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls38 ws4b">©<span class="_ _0"></span>2002 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>2/02<span class="_ _a"> </span>399</span></div><div class="t m0 x2 h5 ycf ff3 fs3 fc0 sc0 ls56 wsa0">Data# Polling (DQ</div><div class="t m0 x1b ha yd0 ff3 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m0 xd h5 ycf ff3 fs3 fc0 sc0 ls3 ws2">)</div><div class="t m0 x2 h6 yd1 ff2 fs0 fc0 sc0 ls30 wsa1">When<span class="_ _0"></span> the S<span class="_ _0"></span>ST39L<span class="_ _0"></span>F/VF1<span class="_ _0"></span>60 a<span class="_ _0"></span>re in<span class="_ _0"></span> the i<span class="_ _0"></span>nter<span class="_ _0"></span>nal<span class="_ _0"></span> Pro<span class="_ _0"></span>gram</div><div class="t m0 x2 h6 yd2 ff2 fs0 fc0 sc0 ls3f wsa2">operatio<span class="_ _0"></span>n, any atte<span class="_ _0"></span>mpt to re<span class="_ _0"></span>ad DQ</div><div class="t m0 x1c h7 yd3 ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x1d h6 yd4 ff2 fs0 fc0 sc0 ls27 wsa3"> will pr<span class="_ _0"></span>oduce<span class="_ _0"></span> the com-</div><div class="t m0 x2 h6 yd5 ff2 fs0 fc0 sc0 ls2e wsa4">plement<span class="_ _0"></span> of the tr<span class="_ _0"></span>ue data. O<span class="_ _0"></span>nce the Pr<span class="_ _0"></span>ogram operation is</div><div class="t m0 x2 h6 yd6 ff2 fs0 fc0 sc0 ls57 wsa5">comp<span class="_ _0"></span>leted<span class="_ _0"></span>, DQ</div><div class="t m0 x12 h7 yd7 ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x1e h6 yd8 ff2 fs0 fc0 sc0 ls58 wsa6"> will pro<span class="_ _0"></span>duce tr<span class="_ _0"></span>ue data<span class="_ _0"></span>. Note that ev<span class="_ _1"></span>en</div><div class="t m0 x2 h6 yd9 ff2 fs0 fc0 sc0 ls59 wsa7">thou<span class="_ _1"></span>gh D<span class="_ _1"></span>Q</div><div class="t m0 x1f h7 yda ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x20 h6 ydb ff2 fs0 fc0 sc0 ls3b wsa8"> may ha<span class="_ _1"></span>ve v<span class="_ _1"></span>alid da<span class="_ _0"></span>ta immed<span class="_ _0"></span>iatel<span class="_ _0"></span>y following the</div><div class="t m0 x2 h6 ydc ff2 fs0 fc0 sc0 ls5a wsa9">comp<span class="_ _0"></span>letion of<span class="_ _0"></span> an inter<span class="_ _0"></span>n<span class="_ _0"></span>al Wr<span class="_ _0"></span>ite operat<span class="_ _0"></span>ion, th<span class="_ _0"></span>e remain<span class="_ _0"></span>ing</div><div class="t m0 x2 h6 ydd ff2 fs0 fc0 sc0 ls27 ws87">data ou<span class="_ _0"></span>tputs may still be invalid: valid data on<span class="_ _0"></span> the enti<span class="_ _0"></span>re</div><div class="t m0 x2 h6 yde ff2 fs0 fc0 sc0 ls3b wsaa">data bus will<span class="_ _0"></span> appea<span class="_ _0"></span>r in subse<span class="_ _0"></span>quent<span class="_ _0"></span> succe<span class="_ _0"></span>ssive Read</div><div class="t m0 x2 h6 ydf ff2 fs0 fc0 sc0 ls2e ws42">cycl<span class="_ _0"></span>es after an i<span class="_ _0"></span>nter<span class="_ _0"></span>val of 1 µs. Dur<span class="_ _0"></span>ing in<span class="_ _0"></span>ter<span class="_ _0"></span>nal<span class="_ _0"></span> Erase opera-</div><div class="t m0 x2 h6 ye0 ff2 fs0 fc0 sc0 ls52 wsab">tion, any a<span class="_ _0"></span>ttempt to<span class="_ _0"></span> read DQ</div><div class="t m0 x21 h7 ye1 ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x22 h6 ye2 ff2 fs0 fc0 sc0 ls23 wsac"> will pro<span class="_ _0"></span>duce <span class="_ _0"></span>a ‘0’. O<span class="_ _0"></span>nce th<span class="_ _0"></span>e</div><div class="t m0 x2 h6 ye3 ff2 fs0 fc0 sc0 ls24 wsad">inter<span class="_ _0"></span>nal<span class="_ _0"></span> Erase operati<span class="_ _0"></span>on is compl<span class="_ _0"></span>eted, DQ</div><div class="t m0 x23 h7 ye4 ff2 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x24 h6 ye5 ff2 fs0 fc0 sc0 ls41 wsae"> will <span class="_ _1"></span>prod<span class="_ _1"></span>uce a</div><div class="t m0 x2 h6 ye6 ff2 fs0 fc0 sc0 ls27 wsaf">‘1’.<span class="_ _0"></span> The Data<span class="_ _0"></span># P<span class="_ _1"></span>olling is<span class="_ _0"></span> v<span class="_ _1"></span>ali<span class="_ _0"></span>d after<span class="_ _0"></span> the r<span class="_ _0"></span>ising e<span class="_ _0"></span>dge of<span class="_ _0"></span> f<span class="_ _1"></span>our<span class="_ _0"></span>t<span class="_ _0"></span>h</div><div class="t m0 x2 h6 ye7 ff2 fs0 fc0 sc0 ls50 ws85">WE# (or<span class="_ _0"></span> CE#) puls<span class="_ _0"></span>e f<span class="_ _1"></span>or Pr<span class="_ _0"></span>ogram operatio<span class="_ _0"></span>n. F<span class="_ _1"></span>or Sect<span class="_ _0"></span>or-,</div><div class="t m0 x2 h6 ye8 ff2 fs0 fc0 sc0 ls2e ws16">Block- or C<span class="_ _0"></span>hip-Eras<span class="_ _0"></span>e, the Data# P<span class="_ _1"></span>oll<span class="_ _0"></span>ing is<span class="_ _0"></span> v<span class="_ _1"></span>alid a<span class="_ _0"></span>fter the<span class="_ _0"></span> ris<span class="_ _0"></span>-</div><div class="t m0 x2 h6 ye9 ff2 fs0 fc0 sc0 ls3b wsb0">ing ed<span class="_ _0"></span>ge of sixt<span class="_ _0"></span>h WE# (or CE<span class="_ _0"></span>#) puls<span class="_ _0"></span>e. See Figur<span class="_ _0"></span>e 5 for</div><div class="t m0 x2 h6 yea ff2 fs0 fc0 sc0 ls2f ws9">Data# P<span class="_ _1"></span>oll<span class="_ _0"></span>ing tim<span class="_ _0"></span>ing dia<span class="_ _0"></span>gram and F<span class="_ _0"></span>igure 1<span class="_ _0"></span>6 f<span class="_ _1"></span>or a fl<span class="_ _0"></span>owchar<span class="_ _9"></span>t.</div><div class="t m0 x2 h5 yeb ff3 fs3 fc0 sc0 ls5b wsb1">Toggle Bit (DQ</div><div class="t m0 x25 ha yec ff3 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m0 x26 h5 yeb ff3 fs3 fc0 sc0 ls3 ws2">)</div><div class="t m0 x2 h6 yed ff2 fs0 fc0 sc0 ls2e wsb2">Duri<span class="_ _0"></span>ng the inte<span class="_ _0"></span>r<span class="_ _0"></span>nal Pro<span class="_ _0"></span>gram or Erase ope<span class="_ _0"></span>ration, any co<span class="_ _0"></span>n-</div><div class="t m0 x2 h6 yee ff2 fs0 fc0 sc0 ls5c wsb3">secutive attemp<span class="_ _0"></span>ts to r<span class="_ _0"></span>ead DQ</div><div class="t m0 x22 h7 yef ff2 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m0 x27 h6 yf0 ff2 fs0 fc0 sc0 ls3b wsb4"> will<span class="_ _0"></span> produ<span class="_ _0"></span>ce a<span class="_ _0"></span>lter<span class="_ _0"></span>na<span class="_ _0"></span>ting 1s</div><div class="t m0 x2 h6 yf1 ff2 fs0 fc0 sc0 ls2d ws6c">and 0s, i.e., toggli<span class="_ _0"></span>ng between 1 an<span class="_ _0"></span>d 0. When<span class="_ _0"></span> the inter<span class="_ _0"></span>nal</div><div class="t m0 x2 h6 yf2 ff2 fs0 fc0 sc0 ls2d wsb5">Program or<span class="_ _0"></span> Erase op<span class="_ _0"></span>eratio<span class="_ _0"></span>n is com<span class="_ _0"></span>plete<span class="_ _0"></span>d, the DQ</div><div class="t m0 x28 h7 yf3 ff2 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m0 x29 h6 yf4 ff2 fs0 fc0 sc0 ls5d ws3d"> bit w<span class="_ _1"></span>ill</div><div class="t m0 x2 h6 yf5 ff2 fs0 fc0 sc0 ls27 wsb6">stop<span class="_ _0"></span> toggling<span class="_ _0"></span>. The T<span class="_ _4"></span>oggle Bi<span class="_ _0"></span>t is valid after th<span class="_ _0"></span>e r<span class="_ _0"></span>ising edge<span class="_ _0"></span> of</div><div class="t m0 x2 h6 yf6 ff2 fs0 fc0 sc0 ls24 ws14">fourt<span class="_ _0"></span>h WE# (<span class="_ _0"></span>or CE#) pu<span class="_ _0"></span>lse for Program operati<span class="_ _0"></span>on. For Sec-</div><div class="t m0 x2 h6 yf7 ff2 fs0 fc0 sc0 ls24 wsb7">tor-, Bl<span class="_ _0"></span>ock- or Chip-E<span class="_ _0"></span>rase, the T<span class="_ _4"></span>oggle Bi<span class="_ _0"></span>t is valid after<span class="_ _0"></span> the</div><div class="t m0 x2 h6 yf8 ff2 fs0 fc0 sc0 ls23 wsac">risi<span class="_ _0"></span>ng ed<span class="_ _0"></span>ge of s<span class="_ _0"></span>ixth W<span class="_ _0"></span>E# (or<span class="_ _0"></span> CE#) <span class="_ _0"></span>pulse. Se<span class="_ _0"></span>e Figu<span class="_ _0"></span>re 6 for</div><div class="t m0 x2 h6 yf9 ff2 fs0 fc0 sc0 ls2a ws0">T<span class="_ _4"></span>oggle Bit<span class="_ _0"></span> timing <span class="_ _0"></span>diagram and F<span class="_ _0"></span>igure<span class="_ _0"></span> 16 for a flowchar<span class="_ _9"></span>t.</div><div class="t m0 x2 h5 yfa ff3 fs3 fc0 sc0 ls56 wsa0">Data Protection</div><div class="t m0 x2 h6 yfb ff2 fs0 fc0 sc0 ls3f wsb8">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 pr<span class="_ _0"></span>ovide bot<span class="_ _0"></span>h hardware<span class="_ _0"></span> and so<span class="_ _0"></span>ftware</div><div class="t m0 x2 h6 yfc ff2 fs0 fc0 sc0 ls2a ws0">features to pro<span class="_ _0"></span>tect nonvolatile da<span class="_ _0"></span>ta from<span class="_ _0"></span> inad<span class="_ _0"></span>v<span class="_ _1"></span>er<span class="_ _0"></span>ten<span class="_ _0"></span>t wr<span class="_ _0"></span>ites.</div><div class="t m0 x9 h5 ycf ff3 fs3 fc0 sc0 ls5e wsb9">Hardware Data <span class="_ _1"></span>Protection</div><div class="t m0 x9 h6 yd1 ff2 fs0 fc0 sc0 ls32 ws3c">Noise/G<span class="_ _0"></span>litch<span class="_ _0"></span> Prote<span class="_ _0"></span>ctio<span class="_ _0"></span>n:<span class="ls5f"> A WE# or <span class="_ _1"></span>CE# <span class="_ _1"></span>pulse <span class="_ _1"></span>of l<span class="_ _1"></span>ess th<span class="_ _1"></span>an 5</span></div><div class="t m0 x9 h6 yd2 ff2 fs0 fc0 sc0 ls2c wsf">ns will<span class="_ _0"></span> not <span class="_ _0"></span>initiat<span class="_ _0"></span>e a wr<span class="_ _0"></span>it<span class="_ _0"></span>e cyc<span class="_ _0"></span>le.</div><div class="t m0 x9 h6 yfd ff2 fs0 fc0 sc0 ls3 ws2">V</div><div class="t m0 x2a h7 yfe ff2 fs4 fc0 sc0 ls3c ws2">DD</div><div class="t m0 x2b h6 yff ff2 fs0 fc0 sc0 ls60 wsba"> P<span class="_ _1"></span>ower Up/Do<span class="_ _1"></span>wn D<span class="_ _0"></span>etection:<span class="ls50 wsbb"> The Wr<span class="_ _0"></span>it<span class="_ _0"></span>e operatio<span class="_ _0"></span>n is</span></div><div class="t m0 x9 h6 y100 ff2 fs0 fc0 sc0 ls2d ws49">inhibi<span class="_ _0"></span>ted when <span class="_ _0"></span>V</div><div class="t m0 xb h7 y6f ff2 fs4 fc0 sc0 ls3c ws2">DD</div><div class="t m0 xc h6 y70 ff2 fs0 fc0 sc0 ls30 ws5e"> is le<span class="_ _0"></span>ss than<span class="_ _0"></span> 1.5V<span class="_ _4"></span>.</div><div class="t m0 x9 h6 y101 ff2 fs0 fc0 sc0 ls27 wsbc">Wr<span class="_ _0"></span>ite In<span class="_ _0"></span>hibit Mo<span class="_ _0"></span>de:</div><div class="t m0 x2c h6 y102 ff2 fs0 fc0 sc0 ls2a ws9e"> F<span class="_ _1"></span>orcing<span class="_ _0"></span> OE# low<span class="_ _1"></span>, CE# high,<span class="_ _0"></span> or WE<span class="_ _0"></span>#</div><div class="t m0 x9 h6 y103 ff2 fs0 fc0 sc0 ls3f wsbd">high will<span class="_ _0"></span> inhibi<span class="_ _0"></span>t the Wr<span class="_ _0"></span>ite ope<span class="_ _0"></span>ration. Thi<span class="_ _0"></span>s prev<span class="_ _1"></span>ents inad<span class="_ _0"></span>v<span class="_ _1"></span>er<span class="_ _9"></span>t-</div><div class="t m0 x9 h6 y104 ff2 fs0 fc0 sc0 ls61 wsbe">ent w<span class="_ _1"></span>rites du<span class="_ _1"></span>ring po<span class="_ _1"></span>we<span class="_ _1"></span>r-up o<span class="_ _1"></span>r po<span class="_ _1"></span>wer-<span class="_ _1"></span>do<span class="_ _1"></span>wn.</div><div class="t m0 x9 h5 y105 ff3 fs3 fc0 sc0 ls62 wsbf">Software Data Protection (SDP)</div><div class="t m0 x9 h6 y106 ff2 fs0 fc0 sc0 ls48 wsc0">The SS<span class="_ _1"></span>T39LF/<span class="_ _1"></span>VF16<span class="_ _1"></span>0 pro<span class="_ _1"></span>vid<span class="_ _1"></span>e the JEDE<span class="_ _1"></span>C appr<span class="_ _1"></span>ov<span class="_ _1"></span>ed<span class="_ _1"></span> Soft-</div><div class="t m0 x9 h6 y107 ff2 fs0 fc0 sc0 ls24 wsc1">ware Data P<span class="_ _0"></span>rotect<span class="_ _0"></span>ion sche<span class="_ _0"></span>me for all da<span class="_ _0"></span>ta alteratio<span class="_ _0"></span>n ope<span class="_ _0"></span>ra-</div><div class="t m0 x9 h6 y108 ff2 fs0 fc0 sc0 ls3b wsc2">tions, i.e., Pr<span class="_ _0"></span>ogram and E<span class="_ _0"></span>rase. Any Pr<span class="_ _0"></span>ogram operat<span class="_ _0"></span>ion</div><div class="t m0 x9 h6 y109 ff2 fs0 fc0 sc0 ls23 wsc3">requir<span class="_ _0"></span>es the incl<span class="_ _0"></span>usion of the<span class="_ _0"></span> three-byte s<span class="_ _0"></span>equence. Th<span class="_ _0"></span>e</div><div class="t m0 x9 h6 y10a ff2 fs0 fc0 sc0 ls23 wsc4">three-<span class="_ _0"></span>byte load se<span class="_ _0"></span>quence i<span class="_ _0"></span>s used<span class="_ _0"></span> to initi<span class="_ _0"></span>ate the<span class="_ _0"></span> Program</div><div class="t m0 x9 h6 y10b ff2 fs0 fc0 sc0 ls2f wsc5">operatio<span class="_ _0"></span>n, providing op<span class="_ _0"></span>timal pr<span class="_ _0"></span>otecti<span class="_ _0"></span>on from in<span class="_ _0"></span>adver<span class="_ _0"></span>tent</div><div class="t m0 x9 h6 y10c ff2 fs0 fc0 sc0 ls3f wsc6">Wr<span class="_ _0"></span>ite op<span class="_ _0"></span>erations, e.g., d<span class="_ _0"></span>uri<span class="_ _0"></span>ng the sy<span class="_ _0"></span>stem power-u<span class="_ _0"></span>p or</div><div class="t m0 x9 h6 y10d ff2 fs0 fc0 sc0 ls63 wsc7">po<span class="_ _1"></span>wer-<span class="_ _1"></span>do<span class="_ _1"></span>wn. An<span class="_ _1"></span>y Er<span class="_ _1"></span>ase ope<span class="_ _1"></span>rati<span class="_ _1"></span>on req<span class="_ _1"></span>uire<span class="_ _1"></span>s the incl<span class="_ _1"></span>usion of</div><div class="t m0 x9 h6 y10e ff2 fs0 fc0 sc0 ls29 wsc8">six-<span class="_ _0"></span>b<span class="_ _1"></span>yte<span class="_ _0"></span> sequenc<span class="_ _0"></span>e. These device<span class="_ _0"></span>s are sh<span class="_ _0"></span>ipped<span class="_ _0"></span> with th<span class="_ _0"></span>e</div><div class="t m0 x9 h6 y10f ff2 fs0 fc0 sc0 ls2e ws5d">Software Da<span class="_ _0"></span>ta Protec<span class="_ _0"></span>tion pe<span class="_ _0"></span>rm<span class="_ _0"></span>anently<span class="_ _0"></span> enabled. Se<span class="_ _0"></span>e T<span class="_ _4"></span>able</div><div class="t m0 x9 h6 y110 ff2 fs0 fc0 sc0 ls2e wsc9">4 for the specifi<span class="_ _0"></span>c software<span class="_ _0"></span> command<span class="_ _0"></span> code<span class="_ _0"></span>s. During S<span class="_ _0"></span>DP</div><div class="t m0 x9 h6 y111 ff2 fs0 fc0 sc0 ls2d wsca">comman<span class="_ _0"></span>d seq<span class="_ _0"></span>uence, inv<span class="_ _1"></span>alid c<span class="_ _0"></span>ommands<span class="_ _0"></span> will a<span class="_ _0"></span>bor<span class="_ _0"></span>t th<span class="_ _0"></span>e</div><div class="t m0 x9 h6 y112 ff2 fs0 fc0 sc0 ls33 wscb">device to Read mode wi<span class="_ _0"></span>thin T</div><div class="t m0 x2d h7 y113 ff2 fs4 fc0 sc0 ls3c ws2">RC</div><div class="t m0 x2e h6 y114 ff2 fs0 fc0 sc0 ls64 wscc">. The conten<span class="_ _0"></span>ts of DQ</div><div class="t m0 x2f h7 y113 ff2 fs4 fc0 sc0 ls65 ws2">15</div><div class="t m0 x30 h6 y114 ff2 fs0 fc0 sc0 ls3 ws2">-</div><div class="t m0 x9 h6 y115 ff2 fs0 fc0 sc0 ls66 ws2">DQ</div><div class="t m0 x31 h7 y116 ff2 fs4 fc0 sc0 ls3 ws2">8</div><div class="t m0 x32 h6 y117 ff2 fs0 fc0 sc0 ls67 wscd"> ca<span class="_ _0"></span>n be V</div><div class="t m0 x33 h7 y116 ff2 fs4 fc0 sc0 ls68 ws2">IL</div><div class="t m0 x34 h6 y117 ff2 fs0 fc0 sc0 ls2d wsa7"> or V</div><div class="t m0 x35 h7 y116 ff2 fs4 fc0 sc0 ls68 ws2">IH</div><div class="t m0 x36 h6 y117 ff2 fs0 fc0 sc0 ls26 wsce">, but no oth<span class="_ _0"></span>er value, during<span class="_ _0"></span> any SDP</div><div class="t m0 x9 h6 y118 ff2 fs0 fc0 sc0 ls2c wsf">comm<span class="_ _0"></span>and seq<span class="_ _0"></span>uenc<span class="_ _0"></span>e.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/bg4.jpg"><div class="t m2 xe h8 y64 ff2 fs5 fc0 sc0 ls3 ws2">4</div><div class="t m2 x2 h6 y1 ff2 fs0 fc0 sc0 ls14 ws49">Data Sheet</div><div class="t m2 xf h9 y65 ff3 fs6 fc0 sc0 ls36 ws4a">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m2 x10 h9 y66 ff3 fs6 fc0 sc0 ls37 ws2">SST39LF160 / SST39VF1<span class="_ _0"></span>60</div><div class="t m2 x2 h3 y2 ff2 fs1 fc0 sc0 ls38 ws4b">©<span class="_ _0"></span>2002 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>2/02<span class="_ _a"> </span>399</span></div><div class="t m2 x2 h5 ycf ff3 fs3 fc0 sc0 ls34 wscf">Common Flash Memory Interface (CFI)</div><div class="t m2 x2 h6 yd1 ff2 fs0 fc0 sc0 ls69 wsd0">The S<span class="_ _1"></span>ST39L<span class="_ _1"></span>F/VF1<span class="_ _1"></span>60 al<span class="_ _1"></span>so cont<span class="_ _1"></span>ain t<span class="_ _1"></span>he CFI i<span class="_ _1"></span>nf<span class="_ _5"></span>or<span class="_ _0"></span>mation<span class="_ _1"></span> to</div><div class="t m2 x2 h6 yd2 ff2 fs0 fc0 sc0 ls26 ws47">descr<span class="_ _0"></span>ibe the<span class="_ _0"></span> character<span class="_ _0"></span>isti<span class="_ _0"></span>cs of the device. In order to enter</div><div class="t m2 x2 h6 y119 ff2 fs0 fc0 sc0 ls6a wsd1">the CF<span class="_ _1"></span>I Query mode, the<span class="_ _1"></span> system mu<span class="_ _1"></span>st load<span class="_ _1"></span> the three-<span class="_ _1"></span>by<span class="_ _1"></span>te</div><div class="t m2 x2 h6 y11a ff2 fs0 fc0 sc0 ls2e wsd2">sequenc<span class="_ _0"></span>e, simil<span class="_ _0"></span>ar to <span class="_ _0"></span>the So<span class="_ _0"></span>ftware ID<span class="_ _0"></span> Ent<span class="_ _0"></span>r<span class="_ _0"></span>y com<span class="_ _0"></span>mand. T<span class="_ _0"></span>he</div><div class="t m2 x2 h6 y11b ff2 fs0 fc0 sc0 ls27 wsd3">last<span class="_ _0"></span> byte cycle o<span class="_ _0"></span>f this c<span class="_ _0"></span>omman<span class="_ _0"></span>d loads<span class="_ _0"></span> 98H (CF<span class="_ _0"></span>I Quer<span class="_ _0"></span>y</div><div class="t m2 x2 h6 y11c ff2 fs0 fc0 sc0 ls27 ws95">comm<span class="_ _0"></span>and) to<span class="_ _0"></span> addre<span class="_ _0"></span>ss 555<span class="_ _0"></span>5H. Onc<span class="_ _0"></span>e th<span class="_ _0"></span>e device ent<span class="_ _0"></span>ers th<span class="_ _0"></span>e</div><div class="t m2 x2 h6 y11d ff2 fs0 fc0 sc0 ls33 wsd4">CFI Quer<span class="_ _0"></span>y mo<span class="_ _0"></span>de, the system can r<span class="_ _0"></span>ead CFI data at<span class="_ _0"></span> the</div><div class="t m2 x2 h6 y11e ff2 fs0 fc0 sc0 ls26 ws5c">addres<span class="_ _0"></span>ses given in T<span class="_ _4"></span>ables 5 thr<span class="_ _0"></span>ough 7.<span class="_ _0"></span> The sy<span class="_ _0"></span>stem mus<span class="_ _0"></span>t</div><div class="t m2 x2 h6 y11f ff2 fs0 fc0 sc0 ls40 wsd5">wri<span class="_ _0"></span>te the CF<span class="_ _0"></span>I Exit <span class="_ _0"></span>comm<span class="_ _0"></span>and to r<span class="_ _0"></span>etur<span class="_ _0"></span>n to<span class="_ _0"></span> Read <span class="_ _0"></span>mode fr<span class="_ _0"></span>om</div><div class="t m2 x2 h6 y120 ff2 fs0 fc0 sc0 ls2d wse">the CFI Quer<span class="_ _0"></span>y mo<span class="_ _0"></span>de.</div><div class="t m2 x2 h5 y121 ff3 fs3 fc0 sc0 ls56 wsa0">Product Identifica<span class="_ _0"></span>tion</div><div class="t m2 x2 h6 y122 ff2 fs0 fc0 sc0 ls5a wsd6">The P<span class="_ _0"></span>roduct<span class="_ _0"></span> Ident<span class="_ _0"></span>ificati<span class="_ _0"></span>on m<span class="_ _0"></span>ode id<span class="_ _0"></span>entifi<span class="_ _0"></span>es the <span class="_ _0"></span>devices as</div><div class="t m2 x2 h6 y123 ff2 fs0 fc0 sc0 ls2d ws49">the SST<span class="_ _0"></span>39LF/VF<span class="_ _0"></span>160 and <span class="_ _0"></span>manufacturer as S<span class="_ _0"></span>ST<span class="_ _4"></span>. This m<span class="_ _0"></span>ode</div><div class="t m2 x2 h6 y124 ff2 fs0 fc0 sc0 ls30 wsd7">may be acces<span class="_ _0"></span>sed by software<span class="_ _0"></span> operation<span class="_ _0"></span>s. Users m<span class="_ _0"></span>ay use</div><div class="t m2 x2 h6 y125 ff2 fs0 fc0 sc0 ls2e ws5d">the Software Pr<span class="_ _0"></span>oduct Id<span class="_ _0"></span>entific<span class="_ _0"></span>ation o<span class="_ _0"></span>peration to iden<span class="_ _0"></span>tify th<span class="_ _0"></span>e</div><div class="t m2 x2 h6 y126 ff2 fs0 fc0 sc0 ls2a ws2c">par<span class="_ _0"></span>t (<span class="_ _0"></span>i.e., using<span class="_ _0"></span> the device ID) whe<span class="_ _0"></span>n using<span class="_ _0"></span> multiple manu-</div><div class="t m2 x2 h6 y127 ff2 fs0 fc0 sc0 ls23 wsd8">facturers in the s<span class="_ _0"></span>ame so<span class="_ _0"></span>ck<span class="_ _1"></span>et. For details, see T<span class="_ _4"></span>able 4 for</div><div class="t m2 x2 h6 y128 ff2 fs0 fc0 sc0 ls2a ws0">software ope<span class="_ _0"></span>ration, Figur<span class="_ _0"></span>e 10 for the Software ID Entr<span class="_ _9"></span>y and</div><div class="t m2 x2 h6 y129 ff2 fs0 fc0 sc0 ls6b wsd9">Read<span class="_ _1"></span> timi<span class="_ _1"></span>ng di<span class="_ _1"></span>agr<span class="_ _1"></span>am,<span class="_ _1"></span> and Fi<span class="_ _1"></span>gure<span class="_ _1"></span> 17 f<span class="_ _1"></span>or t<span class="_ _1"></span>he Sof<span class="_ _1"></span>twa<span class="_ _1"></span>re ID</div><div class="t m2 x2 h6 y12a ff2 fs0 fc0 sc0 ls4a wsda">Entry comman<span class="_ _1"></span>d seque<span class="_ _1"></span>nce flo<span class="_ _1"></span>wch<span class="_ _1"></span>ar<span class="_ _0"></span>t.</div><div class="t m2 x9 h5 y12b ff3 fs3 fc0 sc0 ls6c wsdb">Product Identification Mode Exit/</div><div class="t m2 x9 h5 y12c ff3 fs3 fc0 sc0 ls6d wsdc">CFI Mode Exit</div><div class="t m2 x9 h6 y12d ff2 fs0 fc0 sc0 ls33 ws7">In ord<span class="_ _0"></span>er to re<span class="_ _0"></span>tur<span class="_ _0"></span>n to<span class="_ _0"></span> the s<span class="_ _0"></span>tandard<span class="_ _0"></span> Read<span class="_ _0"></span> mode, the <span class="_ _0"></span>Software</div><div class="t m2 x9 h6 y12e ff2 fs0 fc0 sc0 ls23 ws6b">Produc<span class="_ _0"></span>t Identifi<span class="_ _0"></span>cation<span class="_ _0"></span> mode must be<span class="_ _0"></span> e<span class="_ _1"></span>xited. Exi<span class="_ _0"></span>t is acco<span class="_ _0"></span>m-</div><div class="t m2 x9 h6 y12f ff2 fs0 fc0 sc0 ls6e wsdd">pli<span class="_ _1"></span>shed b<span class="_ _1"></span>y issu<span class="_ _1"></span>ing th<span class="_ _1"></span>e Soft<span class="_ _1"></span>war<span class="_ _1"></span>e ID Exi<span class="_ _1"></span>t comma<span class="_ _1"></span>nd</div><div class="t m2 x9 h6 y130 ff2 fs0 fc0 sc0 ls27 wsd3">sequ<span class="_ _0"></span>ence, which<span class="_ _0"></span> retur<span class="_ _0"></span>ns t<span class="_ _0"></span>he device to the Re<span class="_ _0"></span>ad mod<span class="_ _0"></span>e.</div><div class="t m2 x9 h6 y131 ff2 fs0 fc0 sc0 ls3b wsde">This co<span class="_ _0"></span>mman<span class="_ _0"></span>d may also<span class="_ _0"></span> be used<span class="_ _0"></span> to res<span class="_ _0"></span>et the<span class="_ _0"></span> device to th<span class="_ _0"></span>e</div><div class="t m2 x9 h6 y132 ff2 fs0 fc0 sc0 ls24 wsdf">Read mod<span class="_ _0"></span>e after a<span class="_ _0"></span>ny inadver<span class="_ _0"></span>ten<span class="_ _0"></span>t transie<span class="_ _0"></span>nt condi<span class="_ _0"></span>tion tha<span class="_ _0"></span>t</div><div class="t m2 x9 h6 y133 ff2 fs0 fc0 sc0 ls26 wse0">appare<span class="_ _0"></span>ntly c<span class="_ _0"></span>auses <span class="_ _0"></span>the device to be<span class="_ _0"></span>hav<span class="_ _1"></span>e abno<span class="_ _0"></span>r<span class="_ _0"></span>mally<span class="_ _5"></span>, e.g.,</div><div class="t m2 x9 h6 y134 ff2 fs0 fc0 sc0 ls23 wsd8">not read<span class="_ _0"></span> corre<span class="_ _0"></span>ctly<span class="_ _4"></span>. Pl<span class="_ _0"></span>eas<span class="_ _0"></span>e note that t<span class="_ _0"></span>he Soft<span class="_ _0"></span>ware ID Exit<span class="_ _0"></span>/</div><div class="t m2 x9 h6 y135 ff2 fs0 fc0 sc0 ls2f wse1">CFI Exit c<span class="_ _0"></span>omma<span class="_ _0"></span>nd is i<span class="_ _0"></span>gnored d<span class="_ _0"></span>uring<span class="_ _0"></span> an int<span class="_ _0"></span>er<span class="_ _0"></span>nal Pr<span class="_ _0"></span>ogram or</div><div class="t m2 x9 h6 y136 ff2 fs0 fc0 sc0 ls27 wse2">Erase op<span class="_ _0"></span>eration. S<span class="_ _0"></span>ee T<span class="_ _4"></span>able 4 for software co<span class="_ _0"></span>mman<span class="_ _0"></span>d</div><div class="t m2 x9 h6 y137 ff2 fs0 fc0 sc0 ls2f ws4e">codes, Figu<span class="_ _0"></span>re 12 for timi<span class="_ _0"></span>ng wav<span class="_ _1"></span>ef<span class="_ _1"></span>or<span class="_ _0"></span>m, an<span class="_ _0"></span>d Figure<span class="_ _0"></span> 17 for a</div><div class="t m2 x9 h6 y138 ff2 fs0 fc0 sc0 ls58 ws2">flowchar<span class="_ _9"></span>t.</div><div class="t m2 x9 h2 y139 ff3 fs0 fc0 sc0 ls6f ws2">T<span class="_ _4"></span>ABLE<span class="_ _7"> </span>1:<span class="_ _c"> </span>P</div><div class="t m2 x37 h2 y13a ff3 fs7 fc0 sc0 ls70 ws2">RODUCT<span class="fs0 ls71"> I</span><span class="ls72">DENT<span class="_ _1"></span>IFIC<span class="_ _1"></span>ATION</span></div><div class="t m2 x38 ha y13b ff3 fs5 fc0 sc0 ls73 ws2">Address<span class="_ _d"> </span>Data</div><div class="t m2 x39 h8 y13c ff2 fs5 fc0 sc0 ls74 wse3">Manuf<span class="_ _5"></span>acturer’<span class="_ _1"></span>s ID<span class="_ _e"> </span>0000H<span class="_ _d"> </span>00BFH</div><div class="t m2 x39 h8 y13d ff2 fs5 fc0 sc0 ls75 wse4">Device ID</div><div class="t m2 x32 h8 y13e ff2 fs5 fc0 sc0 ls76 ws2">SST39LF/VF16<span class="_ _1"></span>0<span class="_ _f"> </span>0001H<span class="_ _10"> </span>2782H</div><div class="t m2 x3a h3 y13f ff2 fs1 fc0 sc0 ls77 ws2">T1.2<span class="_ _11"> </span>399</div><div class="t m3 x3b hb y140 ff2 fs8 fc0 sc0 ls3 ws2">Y<span class="_ _4"></span>-Decoder</div><div class="t m3 x3c hb y141 ff2 fs8 fc0 sc0 ls3 ws2">I/O Buff<span class="_ _1"></span>ers and Data Latches</div><div class="t m4 x38 hc y142 ff2 fs9 fc0 sc0 ls3 ws2">399 ILL B1.1</div><div class="t m3 x1d hb y143 ff2 fs8 fc0 sc0 ls3 ws2">Address Buff<span class="_ _1"></span>er & Latches</div><div class="t m3 x3d hb y144 ff2 fs8 fc0 sc0 ls3 ws2">X-Decoder</div><div class="t m3 x19 hb y145 ff2 fs8 fc0 sc0 ls3 ws2">DQ</div><div class="t m3 x3e hb y146 ff2 fs8 fc0 sc0 ls3 ws2">15</div><div class="t m3 x3f hb y145 ff2 fs8 fc0 sc0 ls3 ws2"> - DQ</div><div class="t m3 x40 hb y146 ff2 fs8 fc0 sc0 ls3 ws2">0</div><div class="t m3 x41 hb y147 ff2 fs8 fc0 sc0 ls3 ws2">Memor<span class="_ _0"></span>y Address</div><div class="t m3 x21 hb y148 ff2 fs8 fc0 sc0 ls3 ws2">OE#</div><div class="t m3 x21 hb y149 ff2 fs8 fc0 sc0 ls3 ws2">CE#</div><div class="t m3 x42 hb y14a ff2 fs8 fc0 sc0 ls78 ws2">WE#</div><div class="t m3 x35 hb y14b ff2 fs8 fc0 sc0 ls3 ws2">SuperFlash</div><div class="t m3 x43 hb y14c ff2 fs8 fc0 sc0 ls3 ws2">Memor<span class="_ _0"></span>y</div><div class="t m3 x44 hb y14d ff2 fs8 fc0 sc0 ls3 ws2">Control Logic</div><div class="t m0 x45 h2 y117 ff3 fs0 fc0 sc0 ls3 ws2">F<span class="fs7 ls79">UNCTIONAL</span><span class="ls71"> B<span class="fs7 ls7a">LOCK</span> D<span class="fs7 ls7b">IAGRAM</span></span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257df0560196e4b84c2a688/bg5.jpg"><div class="t m0 x1a h6 y1 ff2 fs0 fc0 sc0 ls54 ws2">Data Shee<span class="_ _0"></span>t</div><div class="t m0 x2 h9 y65 ff3 fs6 fc0 sc0 ls36 ws4a">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m0 x2 h9 y66 ff3 fs6 fc0 sc0 ls55 ws9f">SST39LF160 / SST39V<span class="_ _0"></span>F160</div><div class="t m0 xe h8 y64 ff2 fs5 fc0 sc0 ls3 ws2">5</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls38 ws4b">©<span class="_ _0"></span>2002 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>2/02<span class="_ _a"> </span>399</span></div><div class="t m0 x46 h2 y14e ff3 fs0 fc0 sc0 ls7c ws2">FIGURE<span class="_ _6"> </span>1:<span class="_ _c"> </span>P<span class="fs7 ls7d">IN</span><span class="ls71"> A<span class="fs7 ls7e">SSIGNME<span class="_ _0"></span>NTS</span><span class="ls3"> <span class="fs7 ls7f">FO<span class="_ _0"></span>R<span class="_ _0"></span></span><span class="ls80 ws0"> 48-</span><span class="fs7 ls7a">LEA<span class="_ _0"></span>D</span><span class="ls81 wse5"> TSOP </span><span class="fs7 ls70">AND</span><span class="ls82 ws7"> 48-</span><span class="fs7 ls83">BALL</span><span class="ls6f wse6"> TFBG<span class="_ _1"></span>A</span></span></span></div><div class="t m0 x2 h2 y14f ff3 fs0 fc0 sc0 ls6f ws2">T<span class="_ _4"></span>ABLE<span class="_ _7"> </span>2:<span class="_ _c"> </span>P</div><div class="t m0 x47 h2 y150 ff3 fs7 fc0 sc0 ls84 ws2">IN<span class="fs0 ls71"> D</span><span class="ls7b">ESCRIPT<span class="_ _1"></span>ION</span></div><div class="t m0 x48 ha y151 ff3 fs5 fc0 sc0 ls85 wse7">Symbol<span class="_ _12"> </span>Pin Name<span class="_ _13"> </span>Functions</div><div class="t m0 x48 h8 y152 ff2 fs5 fc0 sc0 ls3 ws2">A</div><div class="t m0 x45 hd y153 ff2 fsa fc0 sc0 ls86 ws2">19</div><div class="t m0 x13 h8 y152 ff2 fs5 fc0 sc0 ls87 ws2">-A</div><div class="t m0 x49 hd y153 ff2 fsa fc0 sc0 ls3 ws2">0</div><div class="t m0 x47 h8 y152 ff2 fs5 fc0 sc0 ls88 wse8">Address In<span class="_ _1"></span>puts<span class="_ _14"> </span>T<span class="_ _4"></span>o pro<span class="_ _1"></span>vide <span class="_ _1"></span>memory addresses<span class="_ _1"></span>. During <span class="_ _1"></span>Sector-Eras<span class="_ _1"></span>e A</div><div class="t m0 x4a hd y153 ff2 fsa fc0 sc0 ls89 ws2">19</div><div class="t m0 x4b h8 y152 ff2 fs5 fc0 sc0 ls87 ws2">-A</div><div class="t m0 x4c hd y153 ff2 fsa fc0 sc0 ls86 ws2">11</div><div class="t m0 x4d h8 y152 ff2 fs5 fc0 sc0 ls8a ws48"> address <span class="_ _1"></span>lines w<span class="_ _1"></span>ill sele<span class="_ _1"></span>ct the </div><div class="t m0 x1d h8 y154 ff2 fs5 fc0 sc0 ls8b wse9">sector<span class="_ _5"></span>. During Bloc<span class="_ _1"></span>k-Eras<span class="_ _1"></span>e, A</div><div class="t m0 x9 hd y155 ff2 fsa fc0 sc0 ls86 ws2">19</div><div class="t m0 x4e h8 y156 ff2 fs5 fc0 sc0 ls87 ws2">-A</div><div class="t m0 x2b hd y155 ff2 fsa fc0 sc0 ls86 ws2">15</div><div class="t m0 x4f h8 y156 ff2 fs5 fc0 sc0 ls8a ws48"> address<span class="_ _1"></span> line wi<span class="_ _1"></span>ll selec<span class="_ _1"></span>t the b<span class="_ _1"></span>loc<span class="_ _1"></span>k.</div><div class="t m0 x48 h8 y157 ff2 fs5 fc0 sc0 ls8c ws2">DQ</div><div class="t m0 x13 hd y158 ff2 fsa fc0 sc0 ls89 ws2">15</div><div class="t m0 x50 h8 y159 ff2 fs5 fc0 sc0 ls73 ws2">-DQ</div><div class="t m0 x51 hd y158 ff2 fsa fc0 sc0 ls3 ws2">0</div><div class="t m0 x47 h8 y159 ff2 fs5 fc0 sc0 ls8d wsea">Data Inpu<span class="_ _1"></span>t/output<span class="_ _15"> </span>T<span class="_ _4"></span>o ou<span class="_ _1"></span>tput data d<span class="_ _1"></span>uring Read c<span class="_ _1"></span>ycles <span class="_ _1"></span>and receiv<span class="_ _1"></span>e i<span class="_ _1"></span>nput data <span class="_ _1"></span>during Write cyc<span class="_ _1"></span>les. </div><div class="t m0 x1d h8 y15a ff2 fs5 fc0 sc0 ls8e wseb">Data i<span class="_ _1"></span>s internally la<span class="_ _1"></span>tched during <span class="_ _1"></span>a Write cycle<span class="_ _1"></span>. </div><div class="t m0 x1d h8 y15b ff2 fs5 fc0 sc0 ls88 wse8">The outp<span class="_ _1"></span>uts are in<span class="_ _1"></span> tri-state whe<span class="_ _1"></span>n OE# or CE<span class="_ _1"></span># is hig<span class="_ _1"></span>h.</div><div class="t m0 x48 h8 y15c ff2 fs5 fc0 sc0 ls74 wse8">CE#<span class="_ _16"> </span>Chip Enab<span class="_ _1"></span>le<span class="_ _17"> </span>T<span class="_ _4"></span>o activ<span class="_ _5"></span>ate the de<span class="_ _1"></span>vice<span class="_ _1"></span> when CE# is<span class="_ _1"></span> low</div><div class="t m0 x48 h8 y15d ff2 fs5 fc0 sc0 ls8f wsec">OE#<span class="_ _18"> </span>Output Ena<span class="_ _1"></span>ble<span class="_ _19"> </span>T<span class="_ _4"></span>o ga<span class="_ _1"></span>te the data<span class="_ _1"></span> output b<span class="_ _1"></span>uff<span class="_ _1"></span>ers</div><div class="t m0 x48 h8 y15e ff2 fs5 fc0 sc0 ls90 wsed">WE#<span class="_ _1a"> </span>Write Enabl<span class="_ _1"></span>e<span class="_ _1b"> </span>T<span class="_ _4"></span>o co<span class="_ _1"></span>ntrol the W<span class="_ _1"></span>rite oper<span class="_ _1"></span>ations</div><div class="t m0 x48 h8 y15f ff2 fs5 fc0 sc0 ls3 ws2">V</div><div class="t m0 x45 hd y160 ff2 fsa fc0 sc0 ls91 ws2">DD</div><div class="t m0 x47 h8 y161 ff2 fs5 fc0 sc0 ls8f wsec">P<span class="_ _1"></span>o<span class="_ _1"></span>wer Sup<span class="_ _1"></span>ply<span class="_ _1c"> </span>T<span class="_ _4"></span>o pro<span class="_ _1"></span>vide <span class="_ _1"></span>powe<span class="_ _1"></span>r supply v<span class="_ _5"></span>oltage: <span class="_ _1d"> </span>3.0-3.6V f<span class="_ _5"></span>or SST39LF160</div><div class="t m0 x52 h8 y162 ff2 fs5 fc0 sc0 ls92 wsee">2.7-3.6V f<span class="_ _1"></span>o<span class="_ _1"></span>r SST39VF160</div><div class="t m0 x48 h8 y163 ff2 fs5 fc0 sc0 ls3 ws2">V</div><div class="t m0 x45 hd y164 ff2 fsa fc0 sc0 ls93 ws2">SS</div><div class="t m0 x47 h8 y165 ff2 fs5 fc0 sc0 ls94 ws2">Ground</div><div class="t m0 x48 h8 y166 ff2 fs5 fc0 sc0 ls95 wsef">NC<span class="_ _1e"> </span>No Connec<span class="_ _1"></span>tion<span class="_ _12"> </span>Unc<span class="_ _1"></span>onnecte<span class="_ _1"></span>d pins</div><div class="t m0 x3a h3 y167 ff2 fs1 fc0 sc0 ls96 wsf0">T2.3 399</div><div class="t m5 x53 he y168 ff2 fsb fc0 sc0 ls3 ws2">A13</div><div class="t m5 x54 he y169 ff2 fsb fc0 sc0 ls3 ws2">A9</div><div class="t m5 x55 he y16a ff2 fsb fc0 sc0 ls3 ws2">WE#</div><div class="t m5 xb he y16b ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x54 he y16c ff2 fsb fc0 sc0 ls3 ws2">A7</div><div class="t m5 x54 he y16d ff2 fsb fc0 sc0 ls3 ws2">A3</div><div class="t m5 x56 he y168 ff2 fsb fc0 sc0 ls3 ws2">A12</div><div class="t m5 x3b he y169 ff2 fsb fc0 sc0 ls3 ws2">A8</div><div class="t m5 x3b he y16a ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x3b he y16b ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x56 he y16c ff2 fsb fc0 sc0 ls3 ws2">A17</div><div class="t m5 x3b he y16d ff2 fsb fc0 sc0 ls3 ws2">A4</div><div class="t m5 x57 he y168 ff2 fsb fc0 sc0 ls3 ws2">A14</div><div class="t m5 x57 he y169 ff2 fsb fc0 sc0 ls3 ws2">A10</div><div class="t m5 x3f he y16a ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x57 he y16b ff2 fsb fc0 sc0 ls3 ws2">A18</div><div class="t m5 x3f he y16c ff2 fsb fc0 sc0 ls3 ws2">A6</div><div class="t m5 x3f he y16d ff2 fsb fc0 sc0 ls3 ws2">A2</div><div class="t m5 x58 he y168 ff2 fsb fc0 sc0 ls3 ws2">A15</div><div class="t m5 x58 he y169 ff2 fsb fc0 sc0 ls3 ws2">A11</div><div class="t m5 x58 he y16a ff2 fsb fc0 sc0 ls3 ws2">A19</div><div class="t m5 x59 he y16b ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x4d he y16c ff2 fsb fc0 sc0 ls3 ws2">A5</div><div class="t m5 x4d he y16d ff2 fsb fc0 sc0 ls3 ws2">A1</div><div class="t m5 x5a he y168 ff2 fsb fc0 sc0 ls3 ws2">A16</div><div class="t m5 x5b he y169 ff2 fsb fc0 sc0 ls3 ws2">DQ7</div><div class="t m5 x5b he y16a ff2 fsb fc0 sc0 ls3 ws2">DQ5</div><div class="t m5 x5b he y16b ff2 fsb fc0 sc0 ls3 ws2">DQ2</div><div class="t m5 x5b he y16c ff2 fsb fc0 sc0 ls3 ws2">DQ0</div><div class="t m5 x5c he y16d ff2 fsb fc0 sc0 ls3 ws2">A0</div><div class="t m5 x5d he y168 ff2 fsb fc0 sc0 ls3 ws2">NC</div><div class="t m5 x5e he y169 ff2 fsb fc0 sc0 ls3 ws2">DQ14</div><div class="t m5 x5e he y16a ff2 fsb fc0 sc0 ls3 ws2">DQ12</div><div class="t m5 x5e he y16b ff2 fsb fc0 sc0 ls3 ws2">DQ10</div><div class="t m5 x5f he y16c ff2 fsb fc0 sc0 ls3 ws2">DQ8</div><div class="t m5 x5f he y16d ff2 fsb fc0 sc0 ls3 ws2">CE#</div><div class="t m5 x60 he y168 ff2 fsb fc0 sc0 ls3 ws2">DQ15</div><div class="t m5 x60 he y169 ff2 fsb fc0 sc0 ls3 ws2">DQ13</div><div class="t m5 x61 he y16a ff2 fsb fc0 sc0 ls3 ws2">V</div><div class="t m5 x62 he y16e ff2 fsb fc0 sc0 ls3 ws2">DD</div><div class="t m5 x60 he y16b ff2 fsb fc0 sc0 ls3 ws2">DQ11</div><div class="t m5 x61 he y16c ff2 fsb fc0 sc0 ls3 ws2">DQ9</div><div class="t m5 x61 he y16d ff2 fsb fc0 sc0 ls3 ws2">OE#</div><div class="t m5 x1 he y168 ff2 fsb fc0 sc0 ls3 ws2">V</div><div class="t m5 x63 he y16f ff2 fsb fc0 sc0 ls3 ws2">SS</div><div class="t m5 x1 he y169 ff2 fsb fc0 sc0 ls3 ws2">DQ6</div><div class="t m5 x1 he y16a ff2 fsb fc0 sc0 ls3 ws2">DQ4</div><div class="t m5 x1 he y16b ff2 fsb fc0 sc0 ls3 ws2">DQ3</div><div class="t m5 x1 he y16c ff2 fsb fc0 sc0 ls3 ws2">DQ1</div><div class="t m5 x1 he y16d ff2 fsb fc0 sc0 ls3 ws2">V</div><div class="t m5 x63 he y170 ff2 fsb fc0 sc0 ls3 ws2">SS</div><div class="t m6 x64 hf y171 ff2 fsc fc0 sc0 ls3 ws2">399 ILL F02a.1</div><div class="t m0 x65 h10 y172 ff2 fsd fc0 sc0 ls97 ws2">SST39LF/VF160</div><div class="t m0 x66 h11 y173 ff2 fse fc0 sc0 ls3 ws2">T<span class="_ _1"></span>OP <span class="_ _1"></span>VIEW (balls f<span class="_ _1"></span>acing down)</div><div class="t m0 x67 h12 y174 ff2 fsf fc0 sc0 ls3 ws2">6</div><div class="t m0 x67 h12 y175 ff2 fsf fc0 sc0 ls3 ws2">5</div><div class="t m0 x67 h12 y176 ff2 fsf fc0 sc0 ls3 ws2">4</div><div class="t m0 x67 h12 y177 ff2 fsf fc0 sc0 ls3 ws2">3</div><div class="t m0 x67 h12 y178 ff2 fsf fc0 sc0 ls3 ws2">2</div><div class="t m0 x67 h12 y179 ff2 fsf fc0 sc0 ls3 ws2">1</div><div class="t m7 x54 h10 y17a ff2 fsd fc0 sc0 ls98 ws2">A B C D E F G H</div><div class="t m4 x46 hc y17b ff2 fs9 fc0 sc0 ls3 ws2">A15</div><div class="t m4 x46 hc y17c ff2 fs9 fc0 sc0 ls3 ws2">A14</div><div class="t m4 x46 hc y17d ff2 fs9 fc0 sc0 ls3 ws2">A13</div><div class="t m4 x46 hc y17e ff2 fs9 fc0 sc0 ls3 ws2">A12</div><div class="t m4 x46 hc y17f ff2 fs9 fc0 sc0 ls3 ws2">A11</div><div class="t m4 x46 hc y180 ff2 fs9 fc0 sc0 ls3 ws2">A10</div><div class="t m4 x68 hc y181 ff2 fs9 fc0 sc0 ls3 ws2">A9</div><div class="t m4 x68 hc y182 ff2 fs9 fc0 sc0 ls3 ws2">A8</div><div class="t m4 x46 hc y183 ff2 fs9 fc0 sc0 ls3 ws2">A19</div><div class="t m4 x8 hc y184 ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x69 hc y185 ff2 fs9 fc0 sc0 ls3 ws2">WE#</div><div class="t m4 x8 hc y186 ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x8 hc y187 ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x8 hc y188 ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x8 hc y189 ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x46 hc y18a ff2 fs9 fc0 sc0 ls3 ws2">A18</div><div class="t m4 x46 hc y18b ff2 fs9 fc0 sc0 ls3 ws2">A17</div><div class="t m4 x68 hc y18c ff2 fs9 fc0 sc0 ls3 ws2">A7</div><div class="t m4 x68 hc y18d ff2 fs9 fc0 sc0 ls3 ws2">A6</div><div class="t m4 x68 hc y18e ff2 fs9 fc0 sc0 ls3 ws2">A5</div><div class="t m4 x68 hc y18f ff2 fs9 fc0 sc0 ls3 ws2">A4</div><div class="t m4 x68 hc y190 ff2 fs9 fc0 sc0 ls3 ws2">A3</div><div class="t m4 x68 hc y191 ff2 fs9 fc0 sc0 ls3 ws2">A2</div><div class="t m4 x68 hc y192 ff2 fs9 fc0 sc0 ls3 ws2">A1</div><div class="t m4 x6a hc y193 ff2 fs9 fc0 sc0 ls3 ws2">1</div><div class="t m4 x6a hc y194 ff2 fs9 fc0 sc0 ls3 ws2">2</div><div class="t m4 x6a hc y195 ff2 fs9 fc0 sc0 ls3 ws2">3</div><div class="t m4 x6a hc y196 ff2 fs9 fc0 sc0 ls3 ws2">4</div><div class="t m4 x6a hc y197 ff2 fs9 fc0 sc0 ls3 ws2">5</div><div class="t m4 x6a hc y198 ff2 fs9 fc0 sc0 ls3 ws2">6</div><div class="t m4 x6a hc y199 ff2 fs9 fc0 sc0 ls3 ws2">7</div><div class="t m4 x6a hc y19a ff2 fs9 fc0 sc0 ls3 ws2">8</div><div class="t m4 x6a hc y19b ff2 fs9 fc0 sc0 ls3 ws2">9</div><div class="t m4 x6a hc y19c ff2 fs9 fc0 sc0 ls3 ws2">10</div><div class="t m4 x6a hc y19d ff2 fs9 fc0 sc0 ls3 ws2">11</div><div class="t m4 x6a hc y19e ff2 fs9 fc0 sc0 ls3 ws2">12</div><div class="t m4 x6a hc y19f ff2 fs9 fc0 sc0 ls3 ws2">13</div><div class="t m4 x6a hc y1a0 ff2 fs9 fc0 sc0 ls3 ws2">14</div><div class="t m4 x6a hc y1a1 ff2 fs9 fc0 sc0 ls3 ws2">15</div><div class="t m4 x6a hc y1a2 ff2 fs9 fc0 sc0 ls3 ws2">16</div><div class="t m4 x6a hc y1a3 ff2 fs9 fc0 sc0 ls3 ws2">17</div><div class="t m4 x6a hc y1a4 ff2 fs9 fc0 sc0 ls3 ws2">18</div><div class="t m4 x6a hc y1a5 ff2 fs9 fc0 sc0 ls3 ws2">19</div><div class="t m4 x6a hc y1a6 ff2 fs9 fc0 sc0 ls3 ws2">20</div><div class="t m4 x6a hc y1a7 ff2 fs9 fc0 sc0 ls3 ws2">21</div><div class="t m4 x6a hc y1a8 ff2 fs9 fc0 sc0 ls3 ws2">22</div><div class="t m4 x6a hc y1a9 ff2 fs9 fc0 sc0 ls3 ws2">23</div><div class="t m4 x6a hc y1aa ff2 fs9 fc0 sc0 ls3 ws2">24</div><div class="t m4 x39 hc y17b ff2 fs9 fc0 sc0 ls3 ws2">A16</div><div class="t m4 x39 hc y17c ff2 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x39 hc y17d ff2 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x4e hc y1ab ff2 fs9 fc0 sc0 ls3 ws2">SS</div><div class="t m4 x39 hc y17e ff2 fs9 fc0 sc0 ls3 ws2">DQ15</div><div class="t m4 x39 hc y17f ff2 fs9 fc0 sc0 ls3 ws2">DQ7</div><div class="t m4 x39 hc y180 ff2 fs9 fc0 sc0 ls3 ws2">DQ14</div><div class="t m4 x39 hc y181 ff2 fs9 fc0 sc0 ls3 ws2">DQ6</div><div class="t m4 x39 hc y182 ff2 fs9 fc0 sc0 ls3 ws2">DQ13</div><div class="t m4 x39 hc y183 ff2 fs9 fc0 sc0 ls3 ws2">DQ5</div><div class="t m4 x39 hc y184 ff2 fs9 fc0 sc0 ls3 ws2">DQ12</div><div class="t m4 x39 hc y185 ff2 fs9 fc0 sc0 ls3 ws2">DQ4</div><div class="t m4 x39 hc y186 ff2 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x4e hc y1ac ff2 fs9 fc0 sc0 ls3 ws2">DD</div><div class="t m4 x39 hc y187 ff2 fs9 fc0 sc0 ls3 ws2">DQ11</div><div class="t m4 x39 hc y188 ff2 fs9 fc0 sc0 ls3 ws2">DQ3</div><div class="t m4 x39 hc y189 ff2 fs9 fc0 sc0 ls3 ws2">DQ10</div><div class="t m4 x39 hc y18a ff2 fs9 fc0 sc0 ls3 ws2">DQ2</div><div class="t m4 x39 hc y18b ff2 fs9 fc0 sc0 ls3 ws2">DQ9</div><div class="t m4 x39 hc y18c ff2 fs9 fc0 sc0 ls3 ws2">DQ1</div><div class="t m4 x39 hc y18d ff2 fs9 fc0 sc0 ls3 ws2">DQ8</div><div class="t m4 x39 hc y18e ff2 fs9 fc0 sc0 ls3 ws2">DQ0</div><div class="t m4 x39 hc y18f ff2 fs9 fc0 sc0 ls3 ws2">OE#</div><div class="t m4 x39 hc y190 ff2 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x4e hc y1ad ff2 fs9 fc0 sc0 ls3 ws2">SS</div><div class="t m4 x39 hc y191 ff2 fs9 fc0 sc0 ls3 ws2">CE#</div><div class="t m4 x39 hc y192 ff2 fs9 fc0 sc0 ls3 ws2">A0</div><div class="t m4 x6b hc y193 ff2 fs9 fc0 sc0 ls3 ws2">48</div><div class="t m4 x6b hc y194 ff2 fs9 fc0 sc0 ls3 ws2">47</div><div class="t m4 x6b hc y195 ff2 fs9 fc0 sc0 ls3 ws2">46</div><div class="t m4 x6b hc y196 ff2 fs9 fc0 sc0 ls3 ws2">45</div><div class="t m4 x6b hc y197 ff2 fs9 fc0 sc0 ls3 ws2">44</div><div class="t m4 x6b hc y198 ff2 fs9 fc0 sc0 ls3 ws2">43</div><div class="t m4 x6b hc y199 ff2 fs9 fc0 sc0 ls3 ws2">42</div><div class="t m4 x6b hc y19a ff2 fs9 fc0 sc0 ls3 ws2">41</div><div class="t m4 x6b hc y19b ff2 fs9 fc0 sc0 ls3 ws2">40</div><div class="t m4 x6b hc y19c ff2 fs9 fc0 sc0 ls3 ws2">39</div><div class="t m4 x6b hc y19d ff2 fs9 fc0 sc0 ls3 ws2">38</div><div class="t m4 x6b hc y19e ff2 fs9 fc0 sc0 ls3 ws2">37</div><div class="t m4 x6b hc y19f ff2 fs9 fc0 sc0 ls3 ws2">36</div><div class="t m4 x6b hc y1a0 ff2 fs9 fc0 sc0 ls3 ws2">35</div><div class="t m4 x6b hc y1a1 ff2 fs9 fc0 sc0 ls3 ws2">34</div><div class="t m4 x6b hc y1a2 ff2 fs9 fc0 sc0 ls3 ws2">33</div><div class="t m4 x6b hc y1a3 ff2 fs9 fc0 sc0 ls3 ws2">32</div><div class="t m4 x6b hc y1a4 ff2 fs9 fc0 sc0 ls3 ws2">31</div><div class="t m4 x6b hc y1a5 ff2 fs9 fc0 sc0 ls3 ws2">30</div><div class="t m4 x6b hc y1a6 ff2 fs9 fc0 sc0 ls3 ws2">29</div><div class="t m4 x6b hc y1a7 ff2 fs9 fc0 sc0 ls3 ws2">28</div><div class="t m4 x6b hc y1a8 ff2 fs9 fc0 sc0 ls3 ws2">27</div><div class="t m4 x6b hc y1a9 ff2 fs9 fc0 sc0 ls3 ws2">26</div><div class="t m4 x6b hc y1aa ff2 fs9 fc0 sc0 ls3 ws2">25</div><div class="t m4 x6c hc y1ae ff2 fs9 fc0 sc0 ls3 ws2">399 ILL F01.2</div><div class="t m0 x6d h10 y1af ff2 fsd fc0 sc0 ls3 ws2">Standard Pinout</div><div class="t m0 x6e h10 y1b0 ff2 fsd fc0 sc0 ls3 wsf1">T<span class="_ _4"></span>op View</div><div class="t m0 x6f h10 y1b1 ff2 fsd fc0 sc0 ls3 ws2">Die Up</div><div class="t m0 x70 h10 y1b2 ff2 fsd fc0 sc0 ls3 ws2">SST39LF160/SST39VF160</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>