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DataSheet for NOR Flash Memory SST Make
39VF1601SST.rar
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Preliminar<span class="_ _0"></span>y Specific<span class="_ _0"></span>ations</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">&#169;<span class="_ _0"></span>2003 Silico<span class="_ _0"></span>n Storage Technology, Inc.</div><div class="t m1 x2 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">S71223-0<span class="_ _1"></span>3-000<span class="_ _2"> </span>11/03</div><div class="t m1 x2 h3 y4 ff2 fs1 fc1 sc0 ls3 ws2">1</div><div class="t m1 x3 h3 y2 ff2 fs1 fc0 sc0 ls4 ws3">The SST logo an<span class="_ _1"></span>d SuperFlash are r<span class="_ _1"></span>egistered tra<span class="_ _1"></span>demarks of Silicon Storage T<span class="_ _3"></span>echnology<span class="_ _3"></span>, Inc.</div><div class="t m1 x4 h3 y3 ff2 fs1 fc0 sc0 ls5 ws4">MPF is a trademark of Silicon Storage T<span class="_ _3"></span>echnology<span class="_ _4"></span>, Inc.</div><div class="t m1 x5 h3 y4 ff2 fs1 fc0 sc0 ls6 ws5">These specif<span class="_ _1"></span>ications are sub<span class="_ _1"></span>ject to change with<span class="_ _1"></span>out notice.</div><div class="t m1 x6 h4 y5 ff1 fs2 fc0 sc0 ls3 ws6">16 Mbit / 32 Mbit<span class="_ _0"></span> / 64 Mbit (x16) Mu<span class="_ _0"></span>lti-Purpose Flash<span class="_ _0"></span> Plus</div><div class="t m1 x7 h5 y6 ff1 fs3 fc0 sc0 ls7 ws7">SST39V<span class="_ _1"></span>F1601 / SST39V<span class="_ _1"></span>F3201 / SST39VF64<span class="_ _1"></span>01</div><div class="t m1 x7 h5 y7 ff1 fs3 fc0 sc0 ls7 ws7">SST39V<span class="_ _1"></span>F1602 / SST39V<span class="_ _1"></span>F3202 / SST39VF64<span class="_ _1"></span>02</div><div class="t m1 x2 h5 y8 ff1 fs3 fc0 sc0 ls8 ws2">FEATURES:</div><div class="t m1 x2 h6 y9 ff1 fs4 fc0 sc0 ls9 ws8">&#8226;<span class="_ _5"> </span>Organized<span class="_ _0"></span> as 1M x1<span class="_ _0"></span>6: SST39V<span class="_ _0"></span>F1601/1<span class="_ _0"></span>602</div><div class="t m1 x8 h6 ya ff1 fs4 fc0 sc0 ls9 ws9">2M x16:<span class="_ _0"></span> SST39VF32<span class="_ _0"></span>01/3202</div><div class="t m1 x8 h6 yb ff1 fs4 fc0 sc0 ls9 ws9">4M x16:<span class="_ _0"></span> SST39VF64<span class="_ _0"></span>01/6402</div><div class="t m1 x2 h6 yc ff1 fs4 fc0 sc0 lsa wsa">&#8226;<span class="_ _5"> </span>Single V<span class="_ _4"></span>oltage Rea<span class="_ _0"></span>d and W<span class="_ _0"></span>rite Operat<span class="_ _0"></span>ions</div><div class="t m1 x9 h7 yd ff2 fs4 fc0 sc0 lsb ws2">&#8211;<span class="_ _6"> </span>2.7-3.6V </div><div class="t m1 x2 h6 ye ff1 fs4 fc0 sc0 lsc wsb">&#8226;<span class="_ _5"> </span>Superior Rel<span class="_ _0"></span>iability</div><div class="t m1 x9 h7 yf ff2 fs4 fc0 sc0 lsd wsc">&#8211;<span class="_ _6"> </span>Endurance<span class="_ _0"></span>: 100,000 Cy<span class="_ _0"></span>cles (T<span class="_ _3"></span>ypical<span class="_ _0"></span>)</div><div class="t m1 x9 h7 y10 ff2 fs4 fc0 sc0 lse wsd">&#8211;<span class="_ _6"> </span>Greater th<span class="_ _0"></span>an 100 years Data<span class="_ _0"></span> Retention</div><div class="t m1 x2 h6 y11 ff1 fs4 fc0 sc0 lsf wse">&#8226;<span class="_ _5"> </span>L<span class="_ _0"></span>ow P<span class="_ _4"></span>ower Co<span class="_ _0"></span>nsumption (typ<span class="_ _0"></span>ical values at 5 MHz)</div><div class="t m1 x9 h7 y12 ff2 fs4 fc0 sc0 lse wsf">&#8211;<span class="_ _6"> </span>Active Current: 9 mA (typical)</div><div class="t m1 x9 h7 y13 ff2 fs4 fc0 sc0 lse wsd">&#8211;<span class="_ _6"> </span>Standby Current<span class="_ _0"></span>: 3 &#181;A (typica<span class="_ _0"></span>l)</div><div class="t m1 x9 h7 y14 ff2 fs4 fc0 sc0 lse wsd">&#8211;<span class="_ _6"> </span>A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er Mode<span class="_ _0"></span>: 3 &#181;A (typi<span class="_ _0"></span>cal)</div><div class="t m1 x2 h6 y15 ff1 fs4 fc0 sc0 ls10 ws10">&#8226;<span class="_ _5"> </span>Hard<span class="_ _4"></span>ware Block-Pr<span class="_ _1"></span>otection/WP# Input P<span class="_ _1"></span>in</div><div class="t m1 x9 h7 y16 ff2 fs4 fc0 sc0 ls11 ws11">&#8211;<span class="_ _6"> </span>T<span class="_ _3"></span>op Block-Protec<span class="_ _0"></span>tion (top<span class="_ _0"></span> 32 KWord)</div><div class="t m1 xa h7 y17 ff2 fs4 fc0 sc0 ls12 ws12">f<span class="_ _1"></span>or SST39V<span class="_ _0"></span>F1602/3202/6<span class="_ _0"></span>402</div><div class="t m1 x9 h7 y18 ff2 fs4 fc0 sc0 ls12 ws13">&#8211;<span class="_ _6"> </span>Bottom Bl<span class="_ _0"></span>ock-Protection <span class="_ _0"></span>(bottom 32<span class="_ _0"></span> KWord)</div><div class="t m1 xa h7 y19 ff2 fs4 fc0 sc0 ls12 ws12">f<span class="_ _1"></span>or SST39V<span class="_ _0"></span>F1601/3201/6<span class="_ _0"></span>401</div><div class="t m1 x2 h6 y1a ff1 fs4 fc0 sc0 ls12 ws13">&#8226;<span class="_ _5"> </span>Sector-Er<span class="_ _0"></span>ase Capabil<span class="_ _0"></span>ity</div><div class="t m1 x9 h7 y1b ff2 fs4 fc0 sc0 ls13 ws14">&#8211;<span class="_ _6"> </span>Uniform<span class="_ _0"></span> 2 KWord sectors</div><div class="t m1 x2 h6 y1c ff1 fs4 fc0 sc0 lsc wsb">&#8226;<span class="_ _5"> </span>Block-Erase Capability</div><div class="t m1 x9 h7 y1d ff2 fs4 fc0 sc0 lsd wsc">&#8211;<span class="_ _6"> </span>Uniform 32<span class="_ _0"></span> KW<span class="_ _1"></span>ord blocks</div><div class="t m1 x2 h6 y1e ff1 fs4 fc0 sc0 ls14 ws15">&#8226;<span class="_ _5"> </span>Chip-Eras<span class="_ _0"></span>e Capability</div><div class="t m1 x2 h6 y1f ff1 fs4 fc0 sc0 ls15 ws16">&#8226;<span class="_ _5"> </span>Erase-<span class="_ _0"></span>Suspend/Er<span class="_ _0"></span>ase-Resu<span class="_ _0"></span>me Capabil<span class="_ _0"></span>ities</div><div class="t m1 x2 h6 y20 ff1 fs4 fc0 sc0 ls16 ws9">&#8226;<span class="_ _5"> </span>Hardware Reset P<span class="_ _0"></span>in (RST#<span class="_ _0"></span>)</div><div class="t m1 xb h6 y21 ff1 fs4 fc0 sc0 ls17 ws17">&#8226;<span class="_ _5"> </span>Security-<span class="_ _0"></span>ID Feature</div><div class="t m1 xc h7 y22 ff2 fs4 fc0 sc0 lsa wsa">&#8211;<span class="_ _6"> </span>SST: 128 bits; U<span class="_ _0"></span>ser<span class="_ _0"></span>: 128 bits</div><div class="t m1 xb h6 y23 ff1 fs4 fc0 sc0 ls18 ws2">&#8226;<span class="_ _5"> </span>Fast Read Access<span class="_ _0"></span> Time:</div><div class="t m1 xc h7 y24 ff2 fs4 fc0 sc0 ls9 ws18">&#8211;<span class="_ _6"> </span>70 ns</div><div class="t m1 xc h7 y25 ff2 fs4 fc0 sc0 ls9 ws18">&#8211;<span class="_ _6"> </span>90 ns</div><div class="t m1 xb h6 y26 ff1 fs4 fc0 sc0 ls19 ws19">&#8226;<span class="_ _5"> </span>Latched Addr<span class="_ _0"></span>ess and Data</div><div class="t m1 xb h6 y27 ff1 fs4 fc0 sc0 ls19 ws19">&#8226;<span class="_ _5"> </span>Fast Erase and<span class="_ _0"></span> W<span class="_ _4"></span>ord-Program:</div><div class="t m1 xc h7 y28 ff2 fs4 fc0 sc0 ls19 ws19">&#8211;<span class="_ _6"> </span>Sector-Erase Tim<span class="_ _0"></span>e: 18 ms (<span class="_ _0"></span>typical)</div><div class="t m1 xc h7 y29 ff2 fs4 fc0 sc0 ls1a ws1a">&#8211;<span class="_ _6"> </span>Blo<span class="_ _0"></span>ck-Eras<span class="_ _0"></span>e Tim<span class="_ _0"></span>e: 18<span class="_ _0"></span> ms<span class="_ _0"></span> (typ<span class="_ _0"></span>ical)</div><div class="t m1 xc h7 y2a ff2 fs4 fc0 sc0 lsd wsc">&#8211;<span class="_ _6"> </span>Chip-Era<span class="_ _0"></span>se Time: 40<span class="_ _0"></span> ms (typic<span class="_ _0"></span>al)</div><div class="t m1 xc h7 y2b ff2 fs4 fc0 sc0 ls1b ws1b">&#8211;<span class="_ _6"> </span>Word-Program Time: 7<span class="_ _0"></span> &#181;s (typ<span class="_ _0"></span>ical)</div><div class="t m1 xb h6 y2c ff1 fs4 fc0 sc0 ls1c ws1c">&#8226;<span class="_ _5"> </span>A<span class="_ _1"></span>utomatic Write Timing</div><div class="t m1 xc h7 y2d ff2 fs4 fc0 sc0 ls1d ws1d">&#8211;<span class="_ _6"> </span>Inter<span class="_ _0"></span>nal V</div><div class="t m1 xd h8 y2e ff2 fs5 fc0 sc0 ls1e ws2">PP</div><div class="t m1 xe h7 y2f ff2 fs4 fc0 sc0 lsd wsc"> Generatio<span class="_ _0"></span>n</div><div class="t m1 xb h6 y30 ff1 fs4 fc0 sc0 ls1f ws1e">&#8226;<span class="_ _5"> </span>End-of-Write Detection</div><div class="t m1 xc h7 y31 ff2 fs4 fc0 sc0 ls20 ws1f">&#8211;<span class="_ _6"> </span>T<span class="_ _3"></span>oggle Bits</div><div class="t m1 xc h7 y32 ff2 fs4 fc0 sc0 ls21 ws20">&#8211;<span class="_ _6"> </span>Data# Polling</div><div class="t m1 xb h6 y33 ff1 fs4 fc0 sc0 lsc wsb">&#8226;<span class="_ _5"> </span>CMOS I<span class="_ _0"></span>/O Compatibility </div><div class="t m1 xb h6 y34 ff1 fs4 fc0 sc0 ls22 ws21">&#8226;<span class="_ _5"> </span>JEDEC Sta<span class="_ _1"></span>ndard</div><div class="t m1 xc h7 y35 ff2 fs4 fc0 sc0 ls23 ws22">&#8211;<span class="_ _6"> </span>Flash <span class="_ _0"></span>EEPROM Pinouts<span class="_ _0"></span> and comm<span class="_ _0"></span>and sets</div><div class="t m1 xb h6 y36 ff1 fs4 fc0 sc0 ls24 ws23">&#8226;<span class="_ _5"> </span>P<span class="_ _4"></span>acka<span class="_ _4"></span>ges A<span class="_ _4"></span>vail<span class="_ _1"></span>ab<span class="_ _1"></span>le</div><div class="t m1 xc h7 y37 ff2 fs4 fc0 sc0 ls16 ws9">&#8211;<span class="_ _6"> </span>48-lead<span class="_ _0"></span> TSOP (12mm<span class="_ _0"></span> x 20mm)</div><div class="t m1 xc h7 y38 ff2 fs4 fc0 sc0 ls11 ws11">&#8211;<span class="_ _6"> </span>48-ball<span class="_ _0"></span> TFBGA (6<span class="_ _0"></span>mm x 8mm<span class="_ _0"></span>) for 16M and 32M</div><div class="t m1 xc h7 y39 ff2 fs4 fc0 sc0 ls25 ws24">&#8211;<span class="_ _6"> </span>48-ball<span class="_ _0"></span> TFBGA (8<span class="_ _0"></span>mm x 10<span class="_ _0"></span>mm) for 64M</div><div class="t m1 x2 h5 y3a ff1 fs3 fc0 sc0 ls26 ws25">PRODUCT DESCRIPTION</div><div class="t m1 x2 h7 y3b ff2 fs4 fc0 sc0 ls27 ws26">The SST39<span class="_ _0"></span>VF160x/32<span class="_ _0"></span>0x/640x devices are 1M<span class="_ _0"></span> x16, 2<span class="_ _0"></span>M</div><div class="t m1 x2 h7 y3c ff2 fs4 fc0 sc0 ls28 ws27">x16, and 4M<span class="_ _0"></span> x16 respectively<span class="_ _3"></span>, CMOS Mul<span class="_ _0"></span>ti-Pur<span class="_ _0"></span>pos<span class="_ _0"></span>e</div><div class="t m1 x2 h7 y3d ff2 fs4 fc0 sc0 ls28 ws28">Flash Plus (<span class="_ _0"></span>MPF+) manufactured with SST&#8217;<span class="_ _1"></span>s propr<span class="_ _0"></span>ietar<span class="_ _0"></span>y<span class="_ _3"></span>,</div><div class="t m1 x2 h7 y3e ff2 fs4 fc0 sc0 ls29 ws29">high perfor<span class="_ _0"></span>mance CMOS S<span class="_ _0"></span>uperFlash techn<span class="_ _0"></span>ology<span class="_ _3"></span>. The</div><div class="t m1 x2 h7 y3f ff2 fs4 fc0 sc0 ls2a ws2a">split-ga<span class="_ _0"></span>te cell des<span class="_ _0"></span>ign and thick-oxide tunneli<span class="_ _0"></span>ng injector</div><div class="t m1 x2 h7 y40 ff2 fs4 fc0 sc0 ls27 ws2b">attain better<span class="_ _0"></span> reliability<span class="_ _0"></span> and manufacturability comp<span class="_ _0"></span>ared</div><div class="t m1 x2 h7 y41 ff2 fs4 fc0 sc0 ls27 ws2c">with alte<span class="_ _0"></span>rnat<span class="_ _0"></span>e approach<span class="_ _0"></span>es. The SST39VF16<span class="_ _0"></span>0x/320x/640x</div><div class="t m1 x2 h7 y42 ff2 fs4 fc0 sc0 ls29 ws2d">write <span class="_ _0"></span>(Program or Erase) with<span class="_ _0"></span> a 2.7-3.6V p<span class="_ _0"></span>ow<span class="_ _1"></span>er suppl<span class="_ _0"></span>y<span class="_ _3"></span>.</div><div class="t m1 x2 h7 y43 ff2 fs4 fc0 sc0 ls29 ws2e">These devices conform to JEDE<span class="_ _0"></span>C standard pin<span class="_ _0"></span>outs f<span class="_ _1"></span>or</div><div class="t m1 x2 h7 y44 ff2 fs4 fc0 sc0 ls2b ws20">x16 mem<span class="_ _0"></span>ories.</div><div class="t m1 x2 h7 y45 ff2 fs4 fc0 sc0 ls2c ws2f">F<span class="_ _1"></span>eatur<span class="_ _0"></span>ing h<span class="_ _0"></span>igh per<span class="_ _0"></span>f<span class="_ _1"></span>or<span class="_ _0"></span>mance <span class="_ _0"></span>Word-Program, the</div><div class="t m1 x2 h7 y46 ff2 fs4 fc0 sc0 ls2d ws30">SST39<span class="_ _0"></span>VF160<span class="_ _0"></span>x/320x/<span class="_ _0"></span>640x<span class="_ _0"></span> de<span class="_ _1"></span>vic<span class="_ _0"></span>es provi<span class="_ _0"></span>de a ty<span class="_ _0"></span>pical<span class="_ _0"></span> Word-</div><div class="t m1 x2 h7 y47 ff2 fs4 fc0 sc0 ls2e ws31">Program time<span class="_ _0"></span> of 7 &#181;sec<span class="_ _0"></span>. These d<span class="_ _0"></span>e<span class="_ _1"></span>vice<span class="_ _0"></span>s use T<span class="_ _3"></span>oggle B<span class="_ _0"></span>it or</div><div class="t m1 x2 h7 y48 ff2 fs4 fc0 sc0 ls2f ws32">Data# P<span class="_ _1"></span>olling<span class="_ _0"></span> to indicat<span class="_ _0"></span>e the com<span class="_ _0"></span>pletion of P<span class="_ _0"></span>rogram opera-</div><div class="t m1 x2 h7 y49 ff2 fs4 fc0 sc0 ls2e ws12">tion. T<span class="_ _3"></span>o p<span class="_ _0"></span>rotect aga<span class="_ _0"></span>inst<span class="_ _0"></span> inadver<span class="_ _0"></span>tent wr<span class="_ _0"></span>ite, they have on-chi<span class="_ _0"></span>p</div><div class="t m1 x2 h7 y4a ff2 fs4 fc0 sc0 ls30 ws33">hardware <span class="_ _0"></span>and Soft<span class="_ _0"></span>ware Data P<span class="_ _0"></span>rotection<span class="_ _0"></span> schemes.</div><div class="t m1 x2 h7 y4b ff2 fs4 fc0 sc0 ls2f ws34">Designe<span class="_ _0"></span>d, manufactured, <span class="_ _0"></span>and tes<span class="_ _0"></span>ted for a wid<span class="_ _0"></span>e spectr<span class="_ _0"></span>um o<span class="_ _0"></span>f</div><div class="t m1 x2 h7 y4c ff2 fs4 fc0 sc0 ls2c ws35">applic<span class="_ _0"></span>ations, these d<span class="_ _0"></span>evices are offered with<span class="_ _0"></span> a guarantee<span class="_ _0"></span>d</div><div class="t m1 x2 h7 y4d ff2 fs4 fc0 sc0 ls2c ws36">typica<span class="_ _0"></span>l enduran<span class="_ _0"></span>ce of 100,0<span class="_ _0"></span>00 cycles. Dat<span class="_ _0"></span>a retenti<span class="_ _0"></span>on is rated</div><div class="t m1 x2 h7 y4e ff2 fs4 fc0 sc0 ls2c ws12">at greater tha<span class="_ _0"></span>n 100 years.</div><div class="t m1 xb h7 y4f ff2 fs4 fc0 sc0 ls2c ws37">The SST3<span class="_ _0"></span>9VF16<span class="_ _0"></span>0x/320x/64<span class="_ _0"></span>0x devices are sui<span class="_ _0"></span>ted for appli-</div><div class="t m1 xb h7 y50 ff2 fs4 fc0 sc0 ls31 ws22">cations<span class="_ _0"></span> that req<span class="_ _0"></span>uire convenient and<span class="_ _0"></span> economi<span class="_ _0"></span>cal upda<span class="_ _0"></span>ting of</div><div class="t m1 xb h7 y51 ff2 fs4 fc0 sc0 ls2c ws38">program, confi<span class="_ _0"></span>guration,<span class="_ _0"></span> or data memor<span class="_ _0"></span>y<span class="_ _4"></span>. F<span class="_ _4"></span>o<span class="_ _0"></span>r all system</div><div class="t m1 xb h7 y52 ff2 fs4 fc0 sc0 ls32 ws39">applic<span class="_ _0"></span>ations, th<span class="_ _0"></span>e<span class="_ _1"></span>y si<span class="_ _0"></span>gnific<span class="_ _0"></span>antly i<span class="_ _0"></span>mprov<span class="_ _1"></span>e p<span class="_ _0"></span>erformanc<span class="_ _0"></span>e and</div><div class="t m1 xb h7 y53 ff2 fs4 fc0 sc0 ls33 ws3a">relia<span class="_ _0"></span>bility<span class="_ _3"></span>,<span class="_ _0"></span> while lower<span class="_ _0"></span>ing power co<span class="_ _0"></span>nsumpti<span class="_ _0"></span>on. They in<span class="_ _0"></span>her-</div><div class="t m1 xb h7 y54 ff2 fs4 fc0 sc0 ls34 ws23">ently <span class="_ _0"></span>use less<span class="_ _0"></span> energy dur<span class="_ _0"></span>ing E<span class="_ _0"></span>rase and P<span class="_ _0"></span>rogram than <span class="_ _0"></span>alter-</div><div class="t m1 xb h7 y55 ff2 fs4 fc0 sc0 ls2e ws3b">native flash te<span class="_ _0"></span>chnolo<span class="_ _0"></span>gies. The total<span class="_ _0"></span> energy consumed<span class="_ _0"></span> is a</div><div class="t m1 xb h7 y56 ff2 fs4 fc0 sc0 ls2e ws13">functio<span class="_ _0"></span>n of th<span class="_ _0"></span>e applied volta<span class="_ _0"></span>ge, current,<span class="_ _0"></span> and time<span class="_ _0"></span> of app<span class="_ _0"></span>lica-</div><div class="t m1 xb h7 y57 ff2 fs4 fc0 sc0 ls2e ws3c">tion. Si<span class="_ _0"></span>nce for any given voltage range, the S<span class="_ _0"></span>uperFla<span class="_ _0"></span>sh</div><div class="t m1 xb h7 y58 ff2 fs4 fc0 sc0 ls2e ws3d">technol<span class="_ _0"></span>og<span class="_ _1"></span>y uses<span class="_ _0"></span> less cur<span class="_ _0"></span>rent to pro<span class="_ _0"></span>gram and has<span class="_ _0"></span> a shor<span class="_ _0"></span>ter</div><div class="t m1 xb h7 y59 ff2 fs4 fc0 sc0 ls34 ws3e">erase time, the tot<span class="_ _0"></span>al energy consu<span class="_ _0"></span>med dur<span class="_ _0"></span>ing any Erase or</div><div class="t m1 xb h7 y5a ff2 fs4 fc0 sc0 ls2c ws35">Program o<span class="_ _0"></span>peration is<span class="_ _0"></span> less th<span class="_ _0"></span>an alter<span class="_ _0"></span>n<span class="_ _0"></span>ative flash tec<span class="_ _0"></span>hnolo-</div><div class="t m1 xb h7 y5b ff2 fs4 fc0 sc0 ls35 ws3f">gies. These<span class="_ _0"></span> devices also<span class="_ _0"></span> improve flex<span class="_ _1"></span>ibi<span class="_ _0"></span>lity whil<span class="_ _0"></span>e lowerin<span class="_ _0"></span>g</div><div class="t m1 xb h7 y5c ff2 fs4 fc0 sc0 ls32 ws40">the cos<span class="_ _0"></span>t for program, data, an<span class="_ _0"></span>d con<span class="_ _0"></span>figuratio<span class="_ _0"></span>n storage ap<span class="_ _0"></span>pli-</div><div class="t m1 xb h7 y5d ff2 fs4 fc0 sc0 ls36 ws2">cations.</div><div class="t m1 xb h7 y5e ff2 fs4 fc0 sc0 ls2a ws14">The SuperFlash technolog<span class="_ _4"></span>y prov<span class="ls37 ws41">ides fix<span class="_ _4"></span>ed Erase and Pro-</span></div><div class="t m1 xb h7 y5f ff2 fs4 fc0 sc0 ls38 ws42">gr<span class="_ _1"></span>am times<span class="_ _1"></span>, independent of the numbe<span class="_ _1"></span>r of Erase/Prog<span class="_ _1"></span>ram</div><div class="t m1 xb h7 y60 ff2 fs4 fc0 sc0 ls39 ws43">cycles that h<span class="_ _1"></span>av<span class="_ _1"></span>e occurred. T<span class="ls3a ws44">heref<span class="_ _4"></span>ore the system software</span></div><div class="t m1 xb h7 y61 ff2 fs4 fc0 sc0 ls3b ws45">or hardwa<span class="_ _1"></span>re does not hav<span class="_ _4"></span>e <span class="_ _0"></span>to be modified or de-r<span class="_ _1"></span>ated as is</div><div class="t m1 xb h7 y62 ff2 fs4 fc0 sc0 ls37 ws46">necessary <span class="_ _0"></span>with alternativ<span class="_ _1"></span>e flash technologies,<span class="_ _1"></span> whose</div><div class="t m1 xb h7 y63 ff2 fs4 fc0 sc0 ls37 ws47">Erase and Prog<span class="_ _1"></span>ram times increase w<span class="_ _1"></span>ith accumulated</div><div class="t m1 xb h7 y64 ff2 fs4 fc0 sc0 ls3c ws48">Erase/Prog<span class="_ _1"></span>ram cycles.</div><div class="t m1 xf h3 y65 ff2 fs1 fc1 sc0 ls3d ws49">SST39VF1<span class="_ _1"></span>60x / 320x / 640x2.7V<span class="_ _1"></span> 16Mb / 32Mb<span class="_ _1"></span> / 64Mb (x16) M<span class="_ _1"></span>PF+ memories</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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