39VF1601SST.rar_memory_nor flash_FlashMX/Flex源码下载-pudn.com

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src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Preliminar<span class="_ _0"></span>y Specific<span class="_ _0"></span>ations</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">©<span class="_ _0"></span>2003 Silico<span class="_ _0"></span>n Storage Technology, Inc.</div><div class="t m1 x2 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">S71223-0<span class="_ _1"></span>3-000<span class="_ _2"> </span>11/03</div><div class="t m1 x2 h3 y4 ff2 fs1 fc1 sc0 ls3 ws2">1</div><div class="t m1 x3 h3 y2 ff2 fs1 fc0 sc0 ls4 ws3">The SST logo an<span class="_ _1"></span>d SuperFlash are r<span class="_ _1"></span>egistered tra<span class="_ _1"></span>demarks of Silicon Storage T<span class="_ _3"></span>echnology<span class="_ _3"></span>, Inc.</div><div class="t m1 x4 h3 y3 ff2 fs1 fc0 sc0 ls5 ws4">MPF is a trademark of Silicon Storage T<span class="_ _3"></span>echnology<span class="_ _4"></span>, Inc.</div><div class="t m1 x5 h3 y4 ff2 fs1 fc0 sc0 ls6 ws5">These specif<span class="_ _1"></span>ications are sub<span class="_ _1"></span>ject to change with<span class="_ _1"></span>out notice.</div><div class="t m1 x6 h4 y5 ff1 fs2 fc0 sc0 ls3 ws6">16 Mbit / 32 Mbit<span class="_ _0"></span> / 64 Mbit (x16) Mu<span class="_ _0"></span>lti-Purpose Flash<span class="_ _0"></span> Plus</div><div class="t m1 x7 h5 y6 ff1 fs3 fc0 sc0 ls7 ws7">SST39V<span class="_ _1"></span>F1601 / SST39V<span class="_ _1"></span>F3201 / SST39VF64<span class="_ _1"></span>01</div><div class="t m1 x7 h5 y7 ff1 fs3 fc0 sc0 ls7 ws7">SST39V<span class="_ _1"></span>F1602 / SST39V<span class="_ _1"></span>F3202 / SST39VF64<span class="_ _1"></span>02</div><div class="t m1 x2 h5 y8 ff1 fs3 fc0 sc0 ls8 ws2">FEATURES:</div><div class="t m1 x2 h6 y9 ff1 fs4 fc0 sc0 ls9 ws8">•<span class="_ _5"> </span>Organized<span class="_ _0"></span> as 1M x1<span class="_ _0"></span>6: SST39V<span class="_ _0"></span>F1601/1<span class="_ _0"></span>602</div><div class="t m1 x8 h6 ya ff1 fs4 fc0 sc0 ls9 ws9">2M x16:<span class="_ _0"></span> SST39VF32<span class="_ _0"></span>01/3202</div><div class="t m1 x8 h6 yb ff1 fs4 fc0 sc0 ls9 ws9">4M x16:<span class="_ _0"></span> SST39VF64<span class="_ _0"></span>01/6402</div><div class="t m1 x2 h6 yc ff1 fs4 fc0 sc0 lsa wsa">•<span class="_ _5"> </span>Single V<span class="_ _4"></span>oltage Rea<span class="_ _0"></span>d and W<span class="_ _0"></span>rite Operat<span class="_ _0"></span>ions</div><div class="t m1 x9 h7 yd ff2 fs4 fc0 sc0 lsb ws2">–<span class="_ _6"> </span>2.7-3.6V </div><div class="t m1 x2 h6 ye ff1 fs4 fc0 sc0 lsc wsb">•<span class="_ _5"> </span>Superior Rel<span class="_ _0"></span>iability</div><div class="t m1 x9 h7 yf ff2 fs4 fc0 sc0 lsd wsc">–<span class="_ _6"> </span>Endurance<span class="_ _0"></span>: 100,000 Cy<span class="_ _0"></span>cles (T<span class="_ _3"></span>ypical<span class="_ _0"></span>)</div><div class="t m1 x9 h7 y10 ff2 fs4 fc0 sc0 lse wsd">–<span class="_ _6"> </span>Greater th<span class="_ _0"></span>an 100 years Data<span class="_ _0"></span> Retention</div><div class="t m1 x2 h6 y11 ff1 fs4 fc0 sc0 lsf wse">•<span class="_ _5"> </span>L<span class="_ _0"></span>ow P<span class="_ _4"></span>ower Co<span class="_ _0"></span>nsumption (typ<span class="_ _0"></span>ical values at 5 MHz)</div><div class="t m1 x9 h7 y12 ff2 fs4 fc0 sc0 lse wsf">–<span class="_ _6"> </span>Active Current: 9 mA (typical)</div><div class="t m1 x9 h7 y13 ff2 fs4 fc0 sc0 lse wsd">–<span class="_ _6"> </span>Standby Current<span class="_ _0"></span>: 3 µA (typica<span class="_ _0"></span>l)</div><div class="t m1 x9 h7 y14 ff2 fs4 fc0 sc0 lse wsd">–<span class="_ _6"> </span>A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er Mode<span class="_ _0"></span>: 3 µA (typi<span class="_ _0"></span>cal)</div><div class="t m1 x2 h6 y15 ff1 fs4 fc0 sc0 ls10 ws10">•<span class="_ _5"> </span>Hard<span class="_ _4"></span>ware Block-Pr<span class="_ _1"></span>otection/WP# Input P<span class="_ _1"></span>in</div><div class="t m1 x9 h7 y16 ff2 fs4 fc0 sc0 ls11 ws11">–<span class="_ _6"> </span>T<span class="_ _3"></span>op Block-Protec<span class="_ _0"></span>tion (top<span class="_ _0"></span> 32 KWord)</div><div class="t m1 xa h7 y17 ff2 fs4 fc0 sc0 ls12 ws12">f<span class="_ _1"></span>or SST39V<span class="_ _0"></span>F1602/3202/6<span class="_ _0"></span>402</div><div class="t m1 x9 h7 y18 ff2 fs4 fc0 sc0 ls12 ws13">–<span class="_ _6"> </span>Bottom Bl<span class="_ _0"></span>ock-Protection <span class="_ _0"></span>(bottom 32<span class="_ _0"></span> KWord)</div><div class="t m1 xa h7 y19 ff2 fs4 fc0 sc0 ls12 ws12">f<span class="_ _1"></span>or SST39V<span class="_ _0"></span>F1601/3201/6<span class="_ _0"></span>401</div><div class="t m1 x2 h6 y1a ff1 fs4 fc0 sc0 ls12 ws13">•<span class="_ _5"> </span>Sector-Er<span class="_ _0"></span>ase Capabil<span class="_ _0"></span>ity</div><div class="t m1 x9 h7 y1b ff2 fs4 fc0 sc0 ls13 ws14">–<span class="_ _6"> </span>Uniform<span class="_ _0"></span> 2 KWord sectors</div><div class="t m1 x2 h6 y1c ff1 fs4 fc0 sc0 lsc wsb">•<span class="_ _5"> </span>Block-Erase Capability</div><div class="t m1 x9 h7 y1d ff2 fs4 fc0 sc0 lsd wsc">–<span class="_ _6"> </span>Uniform 32<span class="_ _0"></span> KW<span class="_ _1"></span>ord blocks</div><div class="t m1 x2 h6 y1e ff1 fs4 fc0 sc0 ls14 ws15">•<span class="_ _5"> </span>Chip-Eras<span class="_ _0"></span>e Capability</div><div class="t m1 x2 h6 y1f ff1 fs4 fc0 sc0 ls15 ws16">•<span class="_ _5"> </span>Erase-<span class="_ _0"></span>Suspend/Er<span class="_ _0"></span>ase-Resu<span class="_ _0"></span>me Capabil<span class="_ _0"></span>ities</div><div class="t m1 x2 h6 y20 ff1 fs4 fc0 sc0 ls16 ws9">•<span class="_ _5"> </span>Hardware Reset P<span class="_ _0"></span>in (RST#<span class="_ _0"></span>)</div><div class="t m1 xb h6 y21 ff1 fs4 fc0 sc0 ls17 ws17">•<span class="_ _5"> </span>Security-<span class="_ _0"></span>ID Feature</div><div class="t m1 xc h7 y22 ff2 fs4 fc0 sc0 lsa wsa">–<span class="_ _6"> </span>SST: 128 bits; U<span class="_ _0"></span>ser<span class="_ _0"></span>: 128 bits</div><div class="t m1 xb h6 y23 ff1 fs4 fc0 sc0 ls18 ws2">•<span class="_ _5"> </span>Fast Read Access<span class="_ _0"></span> Time:</div><div class="t m1 xc h7 y24 ff2 fs4 fc0 sc0 ls9 ws18">–<span class="_ _6"> </span>70 ns</div><div class="t m1 xc h7 y25 ff2 fs4 fc0 sc0 ls9 ws18">–<span class="_ _6"> </span>90 ns</div><div class="t m1 xb h6 y26 ff1 fs4 fc0 sc0 ls19 ws19">•<span class="_ _5"> </span>Latched Addr<span class="_ _0"></span>ess and Data</div><div class="t m1 xb h6 y27 ff1 fs4 fc0 sc0 ls19 ws19">•<span class="_ _5"> </span>Fast Erase and<span class="_ _0"></span> W<span class="_ _4"></span>ord-Program:</div><div class="t m1 xc h7 y28 ff2 fs4 fc0 sc0 ls19 ws19">–<span class="_ _6"> </span>Sector-Erase Tim<span class="_ _0"></span>e: 18 ms (<span class="_ _0"></span>typical)</div><div class="t m1 xc h7 y29 ff2 fs4 fc0 sc0 ls1a ws1a">–<span class="_ _6"> </span>Blo<span class="_ _0"></span>ck-Eras<span class="_ _0"></span>e Tim<span class="_ _0"></span>e: 18<span class="_ _0"></span> ms<span class="_ _0"></span> (typ<span class="_ _0"></span>ical)</div><div class="t m1 xc h7 y2a ff2 fs4 fc0 sc0 lsd wsc">–<span class="_ _6"> </span>Chip-Era<span class="_ _0"></span>se Time: 40<span class="_ _0"></span> ms (typic<span class="_ _0"></span>al)</div><div class="t m1 xc h7 y2b ff2 fs4 fc0 sc0 ls1b ws1b">–<span class="_ _6"> </span>Word-Program Time: 7<span class="_ _0"></span> µs (typ<span class="_ _0"></span>ical)</div><div class="t m1 xb h6 y2c ff1 fs4 fc0 sc0 ls1c ws1c">•<span class="_ _5"> </span>A<span class="_ _1"></span>utomatic Write Timing</div><div class="t m1 xc h7 y2d ff2 fs4 fc0 sc0 ls1d ws1d">–<span class="_ _6"> </span>Inter<span class="_ _0"></span>nal V</div><div class="t m1 xd h8 y2e ff2 fs5 fc0 sc0 ls1e ws2">PP</div><div class="t m1 xe h7 y2f ff2 fs4 fc0 sc0 lsd wsc"> Generatio<span class="_ _0"></span>n</div><div class="t m1 xb h6 y30 ff1 fs4 fc0 sc0 ls1f ws1e">•<span class="_ _5"> </span>End-of-Write Detection</div><div class="t m1 xc h7 y31 ff2 fs4 fc0 sc0 ls20 ws1f">–<span class="_ _6"> </span>T<span class="_ _3"></span>oggle Bits</div><div class="t m1 xc h7 y32 ff2 fs4 fc0 sc0 ls21 ws20">–<span class="_ _6"> </span>Data# Polling</div><div class="t m1 xb h6 y33 ff1 fs4 fc0 sc0 lsc wsb">•<span class="_ _5"> </span>CMOS I<span class="_ _0"></span>/O Compatibility </div><div class="t m1 xb h6 y34 ff1 fs4 fc0 sc0 ls22 ws21">•<span class="_ _5"> </span>JEDEC Sta<span class="_ _1"></span>ndard</div><div class="t m1 xc h7 y35 ff2 fs4 fc0 sc0 ls23 ws22">–<span class="_ _6"> </span>Flash <span class="_ _0"></span>EEPROM Pinouts<span class="_ _0"></span> and comm<span class="_ _0"></span>and sets</div><div class="t m1 xb h6 y36 ff1 fs4 fc0 sc0 ls24 ws23">•<span class="_ _5"> </span>P<span class="_ _4"></span>acka<span class="_ _4"></span>ges A<span class="_ _4"></span>vail<span class="_ _1"></span>ab<span class="_ _1"></span>le</div><div class="t m1 xc h7 y37 ff2 fs4 fc0 sc0 ls16 ws9">–<span class="_ _6"> </span>48-lead<span class="_ _0"></span> TSOP (12mm<span class="_ _0"></span> x 20mm)</div><div class="t m1 xc h7 y38 ff2 fs4 fc0 sc0 ls11 ws11">–<span class="_ _6"> </span>48-ball<span class="_ _0"></span> TFBGA (6<span class="_ _0"></span>mm x 8mm<span class="_ _0"></span>) for 16M and 32M</div><div class="t m1 xc h7 y39 ff2 fs4 fc0 sc0 ls25 ws24">–<span class="_ _6"> </span>48-ball<span class="_ _0"></span> TFBGA (8<span class="_ _0"></span>mm x 10<span class="_ _0"></span>mm) for 64M</div><div class="t m1 x2 h5 y3a ff1 fs3 fc0 sc0 ls26 ws25">PRODUCT DESCRIPTION</div><div class="t m1 x2 h7 y3b ff2 fs4 fc0 sc0 ls27 ws26">The SST39<span class="_ _0"></span>VF160x/32<span class="_ _0"></span>0x/640x devices are 1M<span class="_ _0"></span> x16, 2<span class="_ _0"></span>M</div><div class="t m1 x2 h7 y3c ff2 fs4 fc0 sc0 ls28 ws27">x16, and 4M<span class="_ _0"></span> x16 respectively<span class="_ _3"></span>, CMOS Mul<span class="_ _0"></span>ti-Pur<span class="_ _0"></span>pos<span class="_ _0"></span>e</div><div class="t m1 x2 h7 y3d ff2 fs4 fc0 sc0 ls28 ws28">Flash Plus (<span class="_ _0"></span>MPF+) manufactured with SST’<span class="_ _1"></span>s propr<span class="_ _0"></span>ietar<span class="_ _0"></span>y<span class="_ _3"></span>,</div><div class="t m1 x2 h7 y3e ff2 fs4 fc0 sc0 ls29 ws29">high perfor<span class="_ _0"></span>mance CMOS S<span class="_ _0"></span>uperFlash techn<span class="_ _0"></span>ology<span class="_ _3"></span>. The</div><div class="t m1 x2 h7 y3f ff2 fs4 fc0 sc0 ls2a ws2a">split-ga<span class="_ _0"></span>te cell des<span class="_ _0"></span>ign and thick-oxide tunneli<span class="_ _0"></span>ng injector</div><div class="t m1 x2 h7 y40 ff2 fs4 fc0 sc0 ls27 ws2b">attain better<span class="_ _0"></span> reliability<span class="_ _0"></span> and manufacturability comp<span class="_ _0"></span>ared</div><div class="t m1 x2 h7 y41 ff2 fs4 fc0 sc0 ls27 ws2c">with alte<span class="_ _0"></span>rnat<span class="_ _0"></span>e approach<span class="_ _0"></span>es. The SST39VF16<span class="_ _0"></span>0x/320x/640x</div><div class="t m1 x2 h7 y42 ff2 fs4 fc0 sc0 ls29 ws2d">write <span class="_ _0"></span>(Program or Erase) with<span class="_ _0"></span> a 2.7-3.6V p<span class="_ _0"></span>ow<span class="_ _1"></span>er suppl<span class="_ _0"></span>y<span class="_ _3"></span>.</div><div class="t m1 x2 h7 y43 ff2 fs4 fc0 sc0 ls29 ws2e">These devices conform to JEDE<span class="_ _0"></span>C standard pin<span class="_ _0"></span>outs f<span class="_ _1"></span>or</div><div class="t m1 x2 h7 y44 ff2 fs4 fc0 sc0 ls2b ws20">x16 mem<span class="_ _0"></span>ories.</div><div class="t m1 x2 h7 y45 ff2 fs4 fc0 sc0 ls2c ws2f">F<span class="_ _1"></span>eatur<span class="_ _0"></span>ing h<span class="_ _0"></span>igh per<span class="_ _0"></span>f<span class="_ _1"></span>or<span class="_ _0"></span>mance <span class="_ _0"></span>Word-Program, the</div><div class="t m1 x2 h7 y46 ff2 fs4 fc0 sc0 ls2d ws30">SST39<span class="_ _0"></span>VF160<span class="_ _0"></span>x/320x/<span class="_ _0"></span>640x<span class="_ _0"></span> de<span class="_ _1"></span>vic<span class="_ _0"></span>es provi<span class="_ _0"></span>de a ty<span class="_ _0"></span>pical<span class="_ _0"></span> Word-</div><div class="t m1 x2 h7 y47 ff2 fs4 fc0 sc0 ls2e ws31">Program time<span class="_ _0"></span> of 7 µsec<span class="_ _0"></span>. These d<span class="_ _0"></span>e<span class="_ _1"></span>vice<span class="_ _0"></span>s use T<span class="_ _3"></span>oggle B<span class="_ _0"></span>it or</div><div class="t m1 x2 h7 y48 ff2 fs4 fc0 sc0 ls2f ws32">Data# P<span class="_ _1"></span>olling<span class="_ _0"></span> to indicat<span class="_ _0"></span>e the com<span class="_ _0"></span>pletion of P<span class="_ _0"></span>rogram opera-</div><div class="t m1 x2 h7 y49 ff2 fs4 fc0 sc0 ls2e ws12">tion. T<span class="_ _3"></span>o p<span class="_ _0"></span>rotect aga<span class="_ _0"></span>inst<span class="_ _0"></span> inadver<span class="_ _0"></span>tent wr<span class="_ _0"></span>ite, they have on-chi<span class="_ _0"></span>p</div><div class="t m1 x2 h7 y4a ff2 fs4 fc0 sc0 ls30 ws33">hardware <span class="_ _0"></span>and Soft<span class="_ _0"></span>ware Data P<span class="_ _0"></span>rotection<span class="_ _0"></span> schemes.</div><div class="t m1 x2 h7 y4b ff2 fs4 fc0 sc0 ls2f ws34">Designe<span class="_ _0"></span>d, manufactured, <span class="_ _0"></span>and tes<span class="_ _0"></span>ted for a wid<span class="_ _0"></span>e spectr<span class="_ _0"></span>um o<span class="_ _0"></span>f</div><div class="t m1 x2 h7 y4c ff2 fs4 fc0 sc0 ls2c ws35">applic<span class="_ _0"></span>ations, these d<span class="_ _0"></span>evices are offered with<span class="_ _0"></span> a guarantee<span class="_ _0"></span>d</div><div class="t m1 x2 h7 y4d ff2 fs4 fc0 sc0 ls2c ws36">typica<span class="_ _0"></span>l enduran<span class="_ _0"></span>ce of 100,0<span class="_ _0"></span>00 cycles. Dat<span class="_ _0"></span>a retenti<span class="_ _0"></span>on is rated</div><div class="t m1 x2 h7 y4e ff2 fs4 fc0 sc0 ls2c ws12">at greater tha<span class="_ _0"></span>n 100 years.</div><div class="t m1 xb h7 y4f ff2 fs4 fc0 sc0 ls2c ws37">The SST3<span class="_ _0"></span>9VF16<span class="_ _0"></span>0x/320x/64<span class="_ _0"></span>0x devices are sui<span class="_ _0"></span>ted for appli-</div><div class="t m1 xb h7 y50 ff2 fs4 fc0 sc0 ls31 ws22">cations<span class="_ _0"></span> that req<span class="_ _0"></span>uire convenient and<span class="_ _0"></span> economi<span class="_ _0"></span>cal upda<span class="_ _0"></span>ting of</div><div class="t m1 xb h7 y51 ff2 fs4 fc0 sc0 ls2c ws38">program, confi<span class="_ _0"></span>guration,<span class="_ _0"></span> or data memor<span class="_ _0"></span>y<span class="_ _4"></span>. F<span class="_ _4"></span>o<span class="_ _0"></span>r all system</div><div class="t m1 xb h7 y52 ff2 fs4 fc0 sc0 ls32 ws39">applic<span class="_ _0"></span>ations, th<span class="_ _0"></span>e<span class="_ _1"></span>y si<span class="_ _0"></span>gnific<span class="_ _0"></span>antly i<span class="_ _0"></span>mprov<span class="_ _1"></span>e p<span class="_ _0"></span>erformanc<span class="_ _0"></span>e and</div><div class="t m1 xb h7 y53 ff2 fs4 fc0 sc0 ls33 ws3a">relia<span class="_ _0"></span>bility<span class="_ _3"></span>,<span class="_ _0"></span> while lower<span class="_ _0"></span>ing power co<span class="_ _0"></span>nsumpti<span class="_ _0"></span>on. They in<span class="_ _0"></span>her-</div><div class="t m1 xb h7 y54 ff2 fs4 fc0 sc0 ls34 ws23">ently <span class="_ _0"></span>use less<span class="_ _0"></span> energy dur<span class="_ _0"></span>ing E<span class="_ _0"></span>rase and P<span class="_ _0"></span>rogram than <span class="_ _0"></span>alter-</div><div class="t m1 xb h7 y55 ff2 fs4 fc0 sc0 ls2e ws3b">native flash te<span class="_ _0"></span>chnolo<span class="_ _0"></span>gies. The total<span class="_ _0"></span> energy consumed<span class="_ _0"></span> is a</div><div class="t m1 xb h7 y56 ff2 fs4 fc0 sc0 ls2e ws13">functio<span class="_ _0"></span>n of th<span class="_ _0"></span>e applied volta<span class="_ _0"></span>ge, current,<span class="_ _0"></span> and time<span class="_ _0"></span> of app<span class="_ _0"></span>lica-</div><div class="t m1 xb h7 y57 ff2 fs4 fc0 sc0 ls2e ws3c">tion. Si<span class="_ _0"></span>nce for any given voltage range, the S<span class="_ _0"></span>uperFla<span class="_ _0"></span>sh</div><div class="t m1 xb h7 y58 ff2 fs4 fc0 sc0 ls2e ws3d">technol<span class="_ _0"></span>og<span class="_ _1"></span>y uses<span class="_ _0"></span> less cur<span class="_ _0"></span>rent to pro<span class="_ _0"></span>gram and has<span class="_ _0"></span> a shor<span class="_ _0"></span>ter</div><div class="t m1 xb h7 y59 ff2 fs4 fc0 sc0 ls34 ws3e">erase time, the tot<span class="_ _0"></span>al energy consu<span class="_ _0"></span>med dur<span class="_ _0"></span>ing any Erase or</div><div class="t m1 xb h7 y5a ff2 fs4 fc0 sc0 ls2c ws35">Program o<span class="_ _0"></span>peration is<span class="_ _0"></span> less th<span class="_ _0"></span>an alter<span class="_ _0"></span>n<span class="_ _0"></span>ative flash tec<span class="_ _0"></span>hnolo-</div><div class="t m1 xb h7 y5b ff2 fs4 fc0 sc0 ls35 ws3f">gies. These<span class="_ _0"></span> devices also<span class="_ _0"></span> improve flex<span class="_ _1"></span>ibi<span class="_ _0"></span>lity whil<span class="_ _0"></span>e lowerin<span class="_ _0"></span>g</div><div class="t m1 xb h7 y5c ff2 fs4 fc0 sc0 ls32 ws40">the cos<span class="_ _0"></span>t for program, data, an<span class="_ _0"></span>d con<span class="_ _0"></span>figuratio<span class="_ _0"></span>n storage ap<span class="_ _0"></span>pli-</div><div class="t m1 xb h7 y5d ff2 fs4 fc0 sc0 ls36 ws2">cations.</div><div class="t m1 xb h7 y5e ff2 fs4 fc0 sc0 ls2a ws14">The SuperFlash technolog<span class="_ _4"></span>y prov<span class="ls37 ws41">ides fix<span class="_ _4"></span>ed Erase and Pro-</span></div><div class="t m1 xb h7 y5f ff2 fs4 fc0 sc0 ls38 ws42">gr<span class="_ _1"></span>am times<span class="_ _1"></span>, independent of the numbe<span class="_ _1"></span>r of Erase/Prog<span class="_ _1"></span>ram</div><div class="t m1 xb h7 y60 ff2 fs4 fc0 sc0 ls39 ws43">cycles that h<span class="_ _1"></span>av<span class="_ _1"></span>e occurred. T<span class="ls3a ws44">heref<span class="_ _4"></span>ore the system software</span></div><div class="t m1 xb h7 y61 ff2 fs4 fc0 sc0 ls3b ws45">or hardwa<span class="_ _1"></span>re does not hav<span class="_ _4"></span>e <span class="_ _0"></span>to be modified or de-r<span class="_ _1"></span>ated as is</div><div class="t m1 xb h7 y62 ff2 fs4 fc0 sc0 ls37 ws46">necessary <span class="_ _0"></span>with alternativ<span class="_ _1"></span>e flash technologies,<span class="_ _1"></span> whose</div><div class="t m1 xb h7 y63 ff2 fs4 fc0 sc0 ls37 ws47">Erase and Prog<span class="_ _1"></span>ram times increase w<span class="_ _1"></span>ith accumulated</div><div class="t m1 xb h7 y64 ff2 fs4 fc0 sc0 ls3c ws48">Erase/Prog<span class="_ _1"></span>ram cycles.</div><div class="t m1 xf h3 y65 ff2 fs1 fc1 sc0 ls3d ws49">SST39VF1<span class="_ _1"></span>60x / 320x / 640x2.7V<span class="_ _1"></span> 16Mb / 32Mb<span class="_ _1"></span> / 64Mb (x16) M<span class="_ _1"></span>PF+ memories</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg2.jpg"><div class="t m2 x10 h9 y66 ff2 fs6 fc0 sc0 ls3 ws2">2</div><div class="t m2 x2 h7 y1 ff2 fs4 fc0 sc0 ls3e ws4a">Prelim<span class="_ _0"></span>inary S<span class="_ _0"></span>peci<span class="_ _0"></span>fication<span class="_ _0"></span>s</div><div class="t m2 x11 ha y67 ff1 fs7 fc0 sc0 ls3f ws4b">16 Mbit / 32 Mbit / 64<span class="_ _0"></span> Mbit Multi-Purpose<span class="_ _0"></span> Flash Plus</div><div class="t m2 x12 ha y68 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1601 / SST<span class="_ _0"></span>39VF3201 / SS<span class="_ _0"></span>T39VF6401</div><div class="t m2 x12 ha y69 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1602 / SST<span class="_ _0"></span>39VF3202 / SS<span class="_ _0"></span>T39VF6402</div><div class="t m2 x2 h3 y2 ff2 fs1 fc0 sc0 ls41 ws4d">©<span class="_ _0"></span>2003 Silicon Sto<span class="_ _0"></span>rage Technology, Inc.<span class="_ _7"> </span><span class="ls2 ws2">S71223-03<span class="_ _1"></span>-000<span class="_ _8"> </span>11/03</span></div><div class="t m2 x2 h7 y6a ff2 fs4 fc0 sc0 ls42 ws4e">T<span class="_ _3"></span>o mee<span class="_ _1"></span>t high density<span class="_ _3"></span>, surf<span class="_ _4"></span>ace mount requ<span class="_ _1"></span>irements<span class="_ _1"></span>, the</div><div class="t m2 x2 h7 y6b ff2 fs4 fc0 sc0 ls42 ws4f">SST39VF16<span class="_ _1"></span>0x/320x<span class="_ _1"></span>/640x are off<span class="_ _4"></span>ered in 48-lead<span class="_ _1"></span> TSOP</div><div class="t m2 x2 h7 y6c ff2 fs4 fc0 sc0 ls42 ws50">and 48-b<span class="_ _1"></span>all TFBGA pac<span class="_ _1"></span>kages<span class="_ _1"></span>. See Figu<span class="_ _1"></span>res 1 and 2 f<span class="_ _1"></span>or</div><div class="t m2 x2 h7 y6d ff2 fs4 fc0 sc0 ls43 ws51">pin assignme<span class="_ _1"></span>nts<span class="_ _1"></span>.</div><div class="t m2 x2 h5 y6e ff1 fs3 fc0 sc0 ls44 ws52">Device<span class="_ _0"></span> Opera<span class="_ _0"></span>tion</div><div class="t m2 x2 h7 y6f ff2 fs4 fc0 sc0 ls45 ws53">Commands<span class="_ _0"></span> are us<span class="_ _0"></span>ed to in<span class="_ _0"></span>itiate th<span class="_ _0"></span>e memor<span class="_ _0"></span>y<span class="_ _0"></span> operation f<span class="_ _0"></span>unc-</div><div class="t m2 x2 h7 y70 ff2 fs4 fc0 sc0 ls2c ws54">tions of<span class="_ _0"></span> the device. Comman<span class="_ _0"></span>ds are wr<span class="_ _0"></span>itten<span class="_ _0"></span> to the d<span class="_ _0"></span>e<span class="_ _1"></span>vice</div><div class="t m2 x2 h7 y71 ff2 fs4 fc0 sc0 ls46 ws55">using s<span class="_ _0"></span>tanda<span class="_ _0"></span>rd microp<span class="_ _0"></span>roces<span class="_ _0"></span>sor wr<span class="_ _0"></span>ite sequ<span class="_ _0"></span>ence<span class="_ _0"></span>s. A com-</div><div class="t m2 x2 h7 y72 ff2 fs4 fc0 sc0 ls2f ws56">mand is<span class="_ _0"></span> written<span class="_ _0"></span> by asser<span class="_ _0"></span>tin<span class="_ _0"></span>g WE# low whil<span class="_ _0"></span>e keeping CE#</div><div class="t m2 x2 h7 y73 ff2 fs4 fc0 sc0 ls32 ws57">low<span class="_ _4"></span>. Th<span class="_ _0"></span>e addr<span class="_ _0"></span>ess bus is <span class="_ _0"></span>latche<span class="_ _0"></span>d on the<span class="_ _0"></span> falling edge<span class="_ _0"></span> of WE<span class="_ _0"></span>#</div><div class="t m2 x2 h7 y74 ff2 fs4 fc0 sc0 ls45 ws58">or CE#, <span class="_ _0"></span>whichev<span class="_ _4"></span>e<span class="_ _0"></span>r occu<span class="_ _0"></span>rs last.<span class="_ _0"></span> The data<span class="_ _0"></span> bus is latche<span class="_ _0"></span>d on</div><div class="t m2 x2 h7 y75 ff2 fs4 fc0 sc0 ls30 ws9">the r<span class="_ _0"></span>ising<span class="_ _0"></span> edge of <span class="_ _0"></span>WE# or CE<span class="_ _0"></span>#, whic<span class="_ _0"></span>he<span class="_ _1"></span>ver occurs fi<span class="_ _0"></span>rst.</div><div class="t m2 x2 h6 y76 ff2 fs4 fc0 sc0 ls31 ws59">The SS<span class="_ _0"></span>T39VF16<span class="_ _0"></span>0x/320x/<span class="_ _0"></span>640x also<span class="_ _0"></span> hav<span class="_ _1"></span>e the <span class="ff1 ls47 ws5a">Au<span class="_ _0"></span>t<span class="_ _0"></span>o L<span class="_ _0"></span>o<span class="_ _0"></span>w</span></div><div class="t m2 x2 h6 y77 ff1 fs4 fc0 sc0 ls48 ws2">Po<span class="_ _0"></span>w<span class="_ _0"></span>e<span class="_ _0"></span>r<span class="_ _9"></span><span class="ff2 ls31 ws5b"> mode w<span class="_ _0"></span>hich<span class="_ _0"></span> puts t<span class="_ _0"></span>he device in <span class="_ _0"></span>a ne<span class="_ _0"></span>ar standby</span></div><div class="t m2 x2 h7 y78 ff2 fs4 fc0 sc0 ls30 ws5c">mode afte<span class="_ _0"></span>r data h<span class="_ _0"></span>as been a<span class="_ _0"></span>ccessed<span class="_ _0"></span> with a valid Rea<span class="_ _0"></span>d</div><div class="t m2 x2 h7 y79 ff2 fs4 fc0 sc0 ls2c ws5d">operatio<span class="_ _0"></span>n. This re<span class="_ _0"></span>duces the I</div><div class="t m2 x13 h8 y7a ff2 fs5 fc0 sc0 ls49 ws2">DD</div><div class="t m2 x14 h7 y7b ff2 fs4 fc0 sc0 ls4a ws5e"> active read curre<span class="_ _0"></span>nt from</div><div class="t m2 x2 h7 y7c ff2 fs4 fc0 sc0 ls35 ws1f">typica<span class="_ _0"></span>lly 9 mA<span class="_ _0"></span> to typica<span class="_ _0"></span>lly 3 µA. Th<span class="_ _0"></span>e A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ower mode</div><div class="t m2 x2 h7 y7d ff2 fs4 fc0 sc0 ls35 ws1f">reduce<span class="_ _0"></span>s the typ<span class="_ _0"></span>ical I</div><div class="t m2 x15 h8 y7e ff2 fs5 fc0 sc0 ls49 ws2">DD</div><div class="t m2 x16 h7 y7f ff2 fs4 fc0 sc0 ls38 ws11"> acti<span class="_ _1"></span>v<span class="_ _1"></span>e re<span class="_ _1"></span>ad cur<span class="_ _1"></span>rent t<span class="_ _1"></span>o t<span class="_ _1"></span>he ra<span class="_ _1"></span>nge<span class="_ _1"></span> of 2</div><div class="t m2 x2 h7 y80 ff2 fs4 fc0 sc0 ls4b ws5f">mA/MHz o<span class="_ _1"></span>f Read cy<span class="_ _1"></span>cle time<span class="_ _1"></span>. The d<span class="_ _1"></span>e<span class="_ _1"></span>vice e<span class="_ _4"></span>xits the A<span class="_ _4"></span>uto Low</div><div class="t m2 x2 h7 y81 ff2 fs4 fc0 sc0 ls45 ws60">P<span class="_ _4"></span>ower mode wi<span class="_ _0"></span>th any address<span class="_ _0"></span> transition<span class="_ _0"></span> or contro<span class="_ _0"></span>l signal</div><div class="t m2 x2 h7 y82 ff2 fs4 fc0 sc0 ls45 ws61">transition<span class="_ _0"></span> used to i<span class="_ _0"></span>nitiate a<span class="_ _0"></span>nother R<span class="_ _0"></span>ead cycle, wi<span class="_ _0"></span>th no</div><div class="t m2 x2 h7 y83 ff2 fs4 fc0 sc0 ls30 ws62">access <span class="_ _0"></span>time pe<span class="_ _0"></span>nalty<span class="_ _3"></span>. N<span class="_ _0"></span>ote th<span class="_ _0"></span>at the device do<span class="_ _0"></span>es not <span class="_ _0"></span>enter</div><div class="t m2 x2 h7 y84 ff2 fs4 fc0 sc0 ls4c ws63">A<span class="_ _1"></span>uto-Lo<span class="_ _1"></span>w P<span class="_ _1"></span>ow<span class="_ _1"></span>er mode after powe<span class="_ _1"></span>r-up with CE# held</div><div class="t m2 x2 h7 y85 ff2 fs4 fc0 sc0 ls35 ws64">stea<span class="_ _0"></span>dily low<span class="_ _4"></span>, un<span class="_ _0"></span>til the fi<span class="_ _0"></span>rst add<span class="_ _0"></span>ress t<span class="_ _0"></span>ransition o<span class="_ _0"></span>r CE# is</div><div class="t m2 x2 h7 y86 ff2 fs4 fc0 sc0 ls4d ws65">driv<span class="_ _4"></span>en high.</div><div class="t m2 x2 h5 y87 ff1 fs3 fc0 sc0 ls4e ws2">Read</div><div class="t m2 x2 h7 y88 ff2 fs4 fc0 sc0 ls4f ws66">The Read<span class="_ _1"></span> oper<span class="_ _1"></span>ation of<span class="_ _1"></span> the SST<span class="_ _1"></span>39VF160x/32<span class="_ _1"></span>0x/640x<span class="_ _1"></span> is</div><div class="t m2 x2 h7 y89 ff2 fs4 fc0 sc0 ls50 ws67">cont<span class="_ _0"></span>rolle<span class="_ _0"></span>d by CE# <span class="_ _0"></span>and O<span class="_ _0"></span>E#, b<span class="_ _0"></span>oth have to be l<span class="_ _0"></span>ow f<span class="_ _1"></span>or t<span class="_ _0"></span>he</div><div class="t m2 x2 h7 y8a ff2 fs4 fc0 sc0 ls43 ws68">system to<span class="_ _1"></span> obtain da<span class="_ _1"></span>ta from t<span class="_ _1"></span>he output<span class="_ _1"></span>s.<span class="_ _1"></span> CE# is used<span class="_ _1"></span> f<span class="_ _1"></span>or</div><div class="t m2 x2 h7 y8b ff2 fs4 fc0 sc0 ls51 ws69">de<span class="_ _1"></span>vice selectio<span class="_ _1"></span>n. When CE# is high,<span class="_ _1"></span> the chip is dese-</div><div class="t m2 x2 h7 y8c ff2 fs4 fc0 sc0 ls52 ws6a">lected an<span class="_ _1"></span>d only standb<span class="_ _4"></span>y power is con<span class="_ _1"></span>sumed. OE#<span class="_ _1"></span> is the</div><div class="t m2 x2 h7 y8d ff2 fs4 fc0 sc0 ls53 ws6b">output<span class="_ _1"></span> control and is used to gat<span class="_ _1"></span>e data from the out<span class="_ _1"></span>put</div><div class="t m2 x2 h7 y8e ff2 fs4 fc0 sc0 ls54 ws6c">pins<span class="_ _1"></span>. The dat<span class="_ _1"></span>a b<span class="_ _1"></span>us is in high<span class="_ _1"></span> impedance<span class="_ _1"></span> state when</div><div class="t m2 x2 h7 y8f ff2 fs4 fc0 sc0 ls55 ws6d">either C<span class="_ _1"></span>E# or OE# is h<span class="_ _1"></span>igh. Ref<span class="_ _4"></span>er to the Rea<span class="_ _1"></span>d cycle timin<span class="_ _1"></span>g</div><div class="t m2 x2 h7 y90 ff2 fs4 fc0 sc0 ls56 ws6e">diagr<span class="_ _4"></span>am fo<span class="_ _1"></span>r fur<span class="_ _0"></span>the<span class="_ _1"></span>r details <span class="_ _1"></span>(Figure <span class="_ _1"></span>3).</div><div class="t m2 x2 h5 y91 ff1 fs3 fc0 sc0 ls57 ws6f">Word-Program<span class="_ _1"></span> Operation</div><div class="t m2 x2 h7 y92 ff2 fs4 fc0 sc0 ls2e ws70">The SS<span class="_ _0"></span>T39VF16<span class="_ _0"></span>0x/320x/6<span class="_ _0"></span>40x a<span class="_ _0"></span>re programme<span class="_ _0"></span>d on a</div><div class="t m2 x2 h7 y93 ff2 fs4 fc0 sc0 ls36 ws71">word-by-word<span class="_ _0"></span> basis. B<span class="_ _0"></span>efore program<span class="_ _0"></span>ming, t<span class="_ _0"></span>he se<span class="_ _0"></span>ctor</div><div class="t m2 x2 h7 y94 ff2 fs4 fc0 sc0 ls45 ws72">where th<span class="_ _0"></span>e word exists must be<span class="_ _0"></span> fully erased<span class="_ _0"></span>. The Pr<span class="_ _0"></span>ogram</div><div class="t m2 x2 h7 y95 ff2 fs4 fc0 sc0 ls46 ws73">operatio<span class="_ _0"></span>n is acc<span class="_ _0"></span>omplis<span class="_ _0"></span>hed in thr<span class="_ _0"></span>ee st<span class="_ _0"></span>eps. The firs<span class="_ _0"></span>t step is</div><div class="t m2 x2 h7 y96 ff2 fs4 fc0 sc0 ls58 ws74">the three<span class="_ _0"></span>-byte load sequen<span class="_ _0"></span>ce f<span class="_ _1"></span>or Soft<span class="_ _0"></span>ware Data Protecti<span class="_ _0"></span>on.</div><div class="t m2 x2 h7 y97 ff2 fs4 fc0 sc0 ls2c ws75">The se<span class="_ _0"></span>cond s<span class="_ _0"></span>tep is to l<span class="_ _0"></span>oad word <span class="_ _0"></span>address <span class="_ _0"></span>and word d<span class="_ _0"></span>ata.</div><div class="t m2 x2 h7 y98 ff2 fs4 fc0 sc0 ls31 ws76">Duri<span class="_ _0"></span>ng the Word-Program<span class="_ _0"></span> operatio<span class="_ _0"></span>n, the add<span class="_ _0"></span>resse<span class="_ _0"></span>s are</div><div class="t m2 x2 h7 y99 ff2 fs4 fc0 sc0 ls2e ws77">latched<span class="_ _0"></span> on the<span class="_ _0"></span> f<span class="_ _4"></span>a<span class="_ _0"></span>lling ed<span class="_ _0"></span>ge of ei<span class="_ _0"></span>ther CE# or<span class="_ _0"></span> WE#, whi<span class="_ _0"></span>ch-</div><div class="t m2 x2 h7 y9a ff2 fs4 fc0 sc0 ls59 ws78">ev<span class="_ _4"></span>e<span class="_ _0"></span>r occur<span class="_ _0"></span>s last.<span class="_ _0"></span> The dat<span class="_ _0"></span>a is latc<span class="_ _0"></span>hed on the<span class="_ _0"></span> ris<span class="_ _0"></span>ing edg<span class="_ _0"></span>e of</div><div class="t m2 x2 h7 y9b ff2 fs4 fc0 sc0 ls2e wsc">either<span class="_ _0"></span> CE# or WE<span class="_ _0"></span>#, whic<span class="_ _0"></span>he<span class="_ _1"></span>ver occurs<span class="_ _0"></span> first. T<span class="_ _0"></span>he third <span class="_ _0"></span>step <span class="_ _0"></span>is</div><div class="t m2 x2 h7 y9c ff2 fs4 fc0 sc0 ls5a ws79">the inte<span class="_ _0"></span>r<span class="_ _0"></span>nal Program<span class="_ _0"></span> operation <span class="_ _0"></span>which i<span class="_ _0"></span>s initi<span class="_ _0"></span>ated afte<span class="_ _0"></span>r the</div><div class="t m2 x2 h7 y9d ff2 fs4 fc0 sc0 ls5b ws7a">risi<span class="_ _0"></span>ng edge <span class="_ _0"></span>of the four<span class="_ _0"></span>th<span class="_ _0"></span> WE# o<span class="_ _0"></span>r CE#, whi<span class="_ _0"></span>chev<span class="_ _1"></span>er occurs</div><div class="t m2 xb h7 y9e ff2 fs4 fc0 sc0 ls35 ws7b">first.<span class="_ _0"></span> The Pro<span class="_ _0"></span>gram operati<span class="_ _0"></span>on, once<span class="_ _0"></span> initia<span class="_ _0"></span>ted, w<span class="_ _0"></span>ill be <span class="_ _0"></span>com-</div><div class="t m2 xb h7 y9f ff2 fs4 fc0 sc0 ls45 ws18">pleted wi<span class="_ _0"></span>thin 10 <span class="_ _0"></span>µs. See Figur<span class="_ _0"></span>es 4 an<span class="_ _0"></span>d 5 f<span class="_ _1"></span>or WE<span class="_ _0"></span># and CE<span class="_ _0"></span>#</div><div class="t m2 xb h7 ya0 ff2 fs4 fc0 sc0 ls33 ws7c">cont<span class="_ _0"></span>rolled Pr<span class="_ _0"></span>ogram operat<span class="_ _0"></span>ion timi<span class="_ _0"></span>ng diagrams a<span class="_ _0"></span>nd Figu<span class="_ _0"></span>re</div><div class="t m2 xb h7 ya1 ff2 fs4 fc0 sc0 ls2e ws77">19 for flowchar<span class="_ _0"></span>ts. Dur<span class="_ _0"></span>ing the<span class="_ _0"></span> Program op<span class="_ _0"></span>eration, th<span class="_ _0"></span>e only</div><div class="t m2 xb h7 ya2 ff2 fs4 fc0 sc0 ls34 ws7d">v<span class="_ _1"></span>alid r<span class="_ _0"></span>eads are D<span class="_ _0"></span>ata# P<span class="_ _1"></span>olli<span class="_ _0"></span>ng and T<span class="_ _3"></span>oggle B<span class="_ _0"></span>it. Dur<span class="_ _0"></span>ing the</div><div class="t m2 xb h7 ya3 ff2 fs4 fc0 sc0 ls32 ws7e">inter<span class="_ _0"></span>nal<span class="_ _0"></span> Program op<span class="_ _0"></span>eration, t<span class="_ _0"></span>he host i<span class="_ _0"></span>s free to p<span class="_ _0"></span>erform a<span class="_ _0"></span>ddi-</div><div class="t m2 xb h7 ya4 ff2 fs4 fc0 sc0 ls5c ws6e">tional ta<span class="_ _0"></span>sks. Any co<span class="_ _0"></span>mmands i<span class="_ _0"></span>ssued d<span class="_ _0"></span>uri<span class="_ _0"></span>ng the<span class="_ _0"></span> inter<span class="_ _0"></span>nal P<span class="_ _0"></span>ro-</div><div class="t m2 xb h7 ya5 ff2 fs4 fc0 sc0 ls28 ws7f">gr<span class="_ _4"></span>am opera<span class="_ _1"></span>tion a<span class="_ _1"></span>re ig<span class="_ _1"></span>nored.<span class="_ _1"></span> During<span class="_ _1"></span> the com<span class="_ _1"></span>mand</div><div class="t m2 xb h7 ya6 ff2 fs4 fc0 sc0 ls35 ws1b">sequ<span class="_ _0"></span>ence, WP#<span class="_ _0"></span> should<span class="_ _0"></span> be stat<span class="_ _0"></span>ically h<span class="_ _0"></span>eld h<span class="_ _0"></span>igh or<span class="_ _0"></span> low<span class="_ _4"></span>.</div><div class="t m2 xb h5 ya7 ff1 fs3 fc0 sc0 ls5d ws80">Sector/Block-Erase<span class="_ _1"></span> Operation</div><div class="t m2 xb h7 ya8 ff2 fs4 fc0 sc0 ls5e ws81">The <span class="_ _1"></span>Sector-<span class="_ _1"></span> (or Bl<span class="_ _1"></span>oc<span class="_ _1"></span>k-) Er<span class="_ _1"></span>ase<span class="_ _1"></span> oper<span class="_ _1"></span>ation<span class="_ _1"></span> allo<span class="_ _1"></span>ws th<span class="_ _1"></span>e syste<span class="_ _1"></span>m</div><div class="t m2 xb h7 ya9 ff2 fs4 fc0 sc0 ls2e ws82">to erase <span class="_ _0"></span>the device on a s<span class="_ _0"></span>ector-by-se<span class="_ _0"></span>ctor (or<span class="_ _0"></span> block-b<span class="_ _1"></span>y-</div><div class="t m2 xb h7 yaa ff2 fs4 fc0 sc0 ls5f ws14">block) basis. The SS<span class="_ _0"></span>T39VF1<span class="_ _0"></span>60x/320<span class="_ _0"></span>x/640<span class="_ _0"></span>x offer both Sec-</div><div class="t m2 xb h7 yab ff2 fs4 fc0 sc0 ls31 ws83">tor-Eras<span class="_ _0"></span>e and Block-Era<span class="_ _0"></span>se mode. T<span class="_ _0"></span>he sect<span class="_ _0"></span>or archit<span class="_ _0"></span>ecture</div><div class="t m2 xb h7 yac ff2 fs4 fc0 sc0 ls60 ws84">is based<span class="_ _0"></span> on unifor<span class="_ _0"></span>m sector<span class="_ _0"></span> size of 2 KW<span class="_ _1"></span>ord. T<span class="_ _0"></span>he Block-</div><div class="t m2 xb h7 yad ff2 fs4 fc0 sc0 ls32 ws28">Erase m<span class="_ _0"></span>ode is b<span class="_ _0"></span>ased on <span class="_ _0"></span>uniform <span class="_ _0"></span>b<span class="_ _1"></span>lock size of 3<span class="_ _0"></span>2 KWord.</div><div class="t m2 xb h7 yae ff2 fs4 fc0 sc0 ls5f ws85">The Sec<span class="_ _0"></span>tor-Eras<span class="_ _0"></span>e operatio<span class="_ _0"></span>n is initi<span class="_ _0"></span>ated by ex<span class="_ _4"></span>e<span class="_ _0"></span>cuting a six<span class="_ _0"></span>-</div><div class="t m2 xb h7 yaf ff2 fs4 fc0 sc0 ls33 ws86">byte command se<span class="_ _0"></span>quence wit<span class="_ _0"></span>h Secto<span class="_ _0"></span>r-Erase comm<span class="_ _0"></span>and</div><div class="t m2 xb h7 yb0 ff2 fs4 fc0 sc0 ls33 ws3f">(30H) a<span class="_ _0"></span>nd sect<span class="_ _0"></span>or addr<span class="_ _0"></span>ess (SA<span class="_ _0"></span>) in the l<span class="_ _0"></span>ast bus cycl<span class="_ _0"></span>e. The</div><div class="t m2 xb h7 yb1 ff2 fs4 fc0 sc0 ls33 ws87">Block-Erase o<span class="_ _0"></span>peration<span class="_ _0"></span> is ini<span class="_ _0"></span>tiated by ex<span class="_ _1"></span>ecutin<span class="_ _0"></span>g a six<span class="_ _0"></span>-byte</div><div class="t m2 xb h7 yb2 ff2 fs4 fc0 sc0 ls31 ws88">comman<span class="_ _0"></span>d seque<span class="_ _0"></span>nce with Block-E<span class="_ _0"></span>rase command<span class="_ _0"></span> (50H)</div><div class="t m2 xb h7 yb3 ff2 fs4 fc0 sc0 ls5f ws89">and block address (<span class="_ _0"></span>BA) in th<span class="_ _0"></span>e last bus cycle. Th<span class="_ _0"></span>e sector or</div><div class="t m2 xb h7 yb4 ff2 fs4 fc0 sc0 ls33 ws8a">block addres<span class="_ _0"></span>s is l<span class="_ _0"></span>atched <span class="_ _0"></span>on the <span class="_ _0"></span>falling edge<span class="_ _0"></span> of <span class="_ _0"></span>the si<span class="_ _0"></span>xth</div><div class="t m2 xb h7 yb5 ff2 fs4 fc0 sc0 ls45 ws8b">WE# pu<span class="_ _0"></span>lse, while<span class="_ _0"></span> the com<span class="_ _0"></span>mand (3<span class="_ _0"></span>0H or 50<span class="_ _0"></span>H) is la<span class="_ _0"></span>tched o<span class="_ _0"></span>n</div><div class="t m2 xb h7 yb6 ff2 fs4 fc0 sc0 ls35 ws8c">the ri<span class="_ _0"></span>sing edg<span class="_ _0"></span>e of the six<span class="_ _0"></span>th WE# puls<span class="_ _0"></span>e. The inter<span class="_ _0"></span>na<span class="_ _0"></span>l Erase</div><div class="t m2 xb h7 yb7 ff2 fs4 fc0 sc0 ls32 ws8d">operatio<span class="_ _0"></span>n begins<span class="_ _0"></span> after <span class="_ _0"></span>the six<span class="_ _0"></span>th WE# <span class="_ _0"></span>pulse. The E<span class="_ _0"></span>nd-of-</div><div class="t m2 xb h7 yb8 ff2 fs4 fc0 sc0 ls32 ws8e">Erase op<span class="_ _0"></span>eration can b<span class="_ _0"></span>e deter<span class="_ _0"></span>m<span class="_ _0"></span>ined usin<span class="_ _0"></span>g eithe<span class="_ _0"></span>r Data#</div><div class="t m2 xb h7 yb9 ff2 fs4 fc0 sc0 ls31 ws8f">P<span class="_ _4"></span>o<span class="_ _0"></span>lling or T<span class="_ _3"></span>oggle Bi<span class="_ _0"></span>t methods. See<span class="_ _0"></span> Figures 9 and<span class="_ _0"></span> 10 f<span class="_ _1"></span>or tim-</div><div class="t m2 xb h7 yba ff2 fs4 fc0 sc0 ls38 ws90">ing<span class="_ _1"></span> wa<span class="_ _1"></span>v<span class="_ _1"></span>ef<span class="_ _4"></span>orms and Figu<span class="_ _1"></span>re 23<span class="_ _1"></span> f<span class="_ _1"></span>or th<span class="_ _1"></span>e fl<span class="_ _1"></span>owc<span class="_ _1"></span>hart. Any<span class="_ _1"></span> com-</div><div class="t m2 xb h7 ybb ff2 fs4 fc0 sc0 ls33 ws91">mands i<span class="_ _0"></span>ssued <span class="_ _0"></span>duri<span class="_ _0"></span>ng the S<span class="_ _0"></span>ector- or<span class="_ _0"></span> Block-Erase<span class="_ _0"></span> operatio<span class="_ _0"></span>n</div><div class="t m2 xb h7 ybc ff2 fs4 fc0 sc0 ls59 ws92">are igno<span class="_ _0"></span>red. When<span class="_ _0"></span> WP# is low<span class="_ _4"></span>, any attem<span class="_ _0"></span>pt to Sector<span class="_ _0"></span>-</div><div class="t m2 xb h7 ybd ff2 fs4 fc0 sc0 ls45 ws93">(Block-) E<span class="_ _0"></span>rase the pr<span class="_ _0"></span>otected<span class="_ _0"></span> bloc<span class="_ _1"></span>k wil<span class="_ _0"></span>l be igno<span class="_ _0"></span>red. Du<span class="_ _0"></span>rin<span class="_ _0"></span>g</div><div class="t m2 xb h7 ybe ff2 fs4 fc0 sc0 ls5f ws94">the com<span class="_ _0"></span>mand <span class="_ _0"></span>sequen<span class="_ _0"></span>ce, WP# s<span class="_ _0"></span>hould b<span class="_ _0"></span>e st<span class="_ _0"></span>aticall<span class="_ _0"></span>y hel<span class="_ _0"></span>d</div><div class="t m2 xb h7 ybf ff2 fs4 fc0 sc0 ls5a ws16">high or<span class="_ _0"></span> low<span class="_ _4"></span>.</div><div class="t m2 xb h5 yc0 ff1 fs3 fc0 sc0 ls61 ws95">Erase-Suspend/Erase-Resume Com<span class="_ _0"></span>mands</div><div class="t m2 xb h7 yc1 ff2 fs4 fc0 sc0 ls32 ws96">The Erase-<span class="_ _0"></span>Suspend op<span class="_ _0"></span>eratio<span class="_ _0"></span>n temporar<span class="_ _0"></span>ily su<span class="_ _0"></span>spends a</div><div class="t m2 xb h7 yc2 ff2 fs4 fc0 sc0 ls62 ws97">Secto<span class="_ _1"></span>r- or<span class="_ _1"></span> Bloc<span class="_ _1"></span>k-Er<span class="_ _1"></span>ase op<span class="_ _1"></span>er<span class="_ _1"></span>ation<span class="_ _1"></span> thus all<span class="_ _1"></span>owi<span class="_ _1"></span>ng dat<span class="_ _1"></span>a to be</div><div class="t m2 xb h7 yc3 ff2 fs4 fc0 sc0 ls2c ws98">read from<span class="_ _0"></span> any memor<span class="_ _0"></span>y<span class="_ _0"></span> locati<span class="_ _0"></span>on, or program<span class="_ _0"></span> data into<span class="_ _0"></span> any</div><div class="t m2 xb h7 yc4 ff2 fs4 fc0 sc0 ls34 ws99">sector<span class="_ _0"></span>/bloc<span class="_ _1"></span>k th<span class="_ _0"></span>at is not s<span class="_ _0"></span>uspende<span class="_ _0"></span>d f<span class="_ _1"></span>or an E<span class="_ _0"></span>rase operati<span class="_ _0"></span>on.</div><div class="t m2 xb h7 yc5 ff2 fs4 fc0 sc0 ls59 ws9a">The op<span class="_ _0"></span>eration i<span class="_ _0"></span>s ex<span class="_ _4"></span>ec<span class="_ _0"></span>uted by is<span class="_ _0"></span>suing on<span class="_ _0"></span>e byte comm<span class="_ _0"></span>and</div><div class="t m2 xb h7 yc6 ff2 fs4 fc0 sc0 ls45 ws9b">sequenc<span class="_ _0"></span>e with<span class="_ _0"></span> Erase-S<span class="_ _0"></span>uspend <span class="_ _0"></span>comman<span class="_ _0"></span>d (B0H).<span class="_ _0"></span> The</div><div class="t m2 xb h7 yc7 ff2 fs4 fc0 sc0 ls63 ws9c">de<span class="_ _4"></span>vice automa<span class="_ _1"></span>ticall<span class="_ _1"></span>y enter<span class="_ _1"></span>s read m<span class="_ _1"></span>ode t<span class="_ _1"></span>ypical<span class="_ _1"></span>ly wit<span class="_ _1"></span>hin 20</div><div class="t m2 xb h7 yc8 ff2 fs4 fc0 sc0 ls33 ws3a">µ<span class="_ _0"></span>s afte<span class="_ _0"></span>r the Erase-Su<span class="_ _0"></span>spen<span class="_ _0"></span>d command<span class="_ _0"></span> had been<span class="_ _0"></span> issued.</div><div class="t m2 xb h7 yc9 ff2 fs4 fc0 sc0 ls2b ws9d">V<span class="_ _4"></span>ali<span class="_ _1"></span>d dat<span class="_ _1"></span>a can <span class="_ _1"></span>be re<span class="_ _1"></span>ad fro<span class="_ _1"></span>m an<span class="_ _1"></span>y se<span class="_ _1"></span>ctor o<span class="_ _1"></span>r b<span class="_ _1"></span>loc<span class="_ _1"></span>k t<span class="_ _1"></span>hat is<span class="_ _1"></span> not</div><div class="t m2 xb h7 yca ff2 fs4 fc0 sc0 ls2c ws75">suspen<span class="_ _0"></span>ded fro<span class="_ _0"></span>m an Era<span class="_ _0"></span>se operati<span class="_ _0"></span>on. Re<span class="_ _0"></span>ading at<span class="_ _0"></span> address</div><div class="t m2 xb h7 ycb ff2 fs4 fc0 sc0 ls32 ws6b">locati<span class="_ _0"></span>on wit<span class="_ _0"></span>hin erase-<span class="_ _0"></span>suspende<span class="_ _0"></span>d secto<span class="_ _0"></span>rs/blocks will ou<span class="_ _0"></span>tput</div><div class="t m2 xb h7 ycc ff2 fs4 fc0 sc0 ls64 ws2">DQ</div><div class="t m2 x17 h8 ycd ff2 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m2 x18 h7 yce ff2 fs4 fc0 sc0 ls34 ws9e"> toggli<span class="_ _0"></span>ng and DQ</div><div class="t m2 x4 h8 ycd ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m2 x19 h7 yce ff2 fs4 fc0 sc0 ls4d ws9f"> at “<span class="_ _1"></span>1”. W<span class="_ _1"></span>hile<span class="_ _1"></span> in E<span class="_ _1"></span>ras<span class="_ _1"></span>e-Sus<span class="_ _1"></span>pend</div><div class="t m2 xb h7 ycf ff2 fs4 fc0 sc0 ls31 wsa0">mode, a W<span class="_ _1"></span>ord-<span class="_ _0"></span>Program operat<span class="_ _0"></span>ion is al<span class="_ _0"></span>lowed e<span class="_ _1"></span>xcept for the</div><div class="t m2 xb h7 yd0 ff2 fs4 fc0 sc0 ls65 wsa1">sect<span class="_ _0"></span>or or block se<span class="_ _0"></span>lect<span class="_ _0"></span>ed for Erase-<span class="_ _0"></span>Suspen<span class="_ _0"></span>d.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg3.jpg"><div class="t m1 x1a h7 y1 ff2 fs4 fc0 sc0 ls66 wsa2">Prelimi<span class="_ _0"></span>nary Spec<span class="_ _0"></span>ificati<span class="_ _0"></span>ons</div><div class="t m1 x2 ha y67 ff1 fs7 fc0 sc0 ls3f ws4b">16 Mbit / 32 Mbit / 64 Mb<span class="_ _0"></span>it Multi-Purpose Fl<span class="_ _0"></span>ash Plus</div><div class="t m1 x2 ha y68 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1601 / SST39<span class="_ _0"></span>VF3201 / SST39<span class="_ _0"></span>VF6401</div><div class="t m1 x2 ha y69 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1602 / SST39<span class="_ _0"></span>VF3202 / SST39<span class="_ _0"></span>VF6402</div><div class="t m1 x10 h9 y66 ff2 fs6 fc0 sc0 ls3 ws2">3</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls41 ws4d">©<span class="_ _0"></span>2003 Silicon Sto<span class="_ _0"></span>rage Technology, Inc.<span class="_ _7"> </span><span class="ls2 ws2">S71223-03<span class="_ _1"></span>-000<span class="_ _8"> </span>11/03</span></div><div class="t m1 x2 h7 y6a ff2 fs4 fc0 sc0 ls67 ws7e">T<span class="_ _3"></span>o resum<span class="_ _0"></span>e Sect<span class="_ _0"></span>or-Era<span class="_ _0"></span>se or Bl<span class="_ _0"></span>ock-Erase op<span class="_ _0"></span>eratio<span class="_ _0"></span>n whi<span class="_ _0"></span>ch has</div><div class="t m1 x2 h7 y6b ff2 fs4 fc0 sc0 ls68 wsa3">been suspe<span class="_ _1"></span>nded t<span class="_ _1"></span>he system<span class="_ _1"></span> must issue<span class="_ _1"></span> Era<span class="_ _1"></span>se Resume</div><div class="t m1 x2 h7 y6c ff2 fs4 fc0 sc0 ls69 wsa4">command<span class="_ _1"></span>. The oper<span class="_ _1"></span>ation is e<span class="_ _4"></span>xe<span class="_ _1"></span>cuted b<span class="_ _1"></span>y issuing one b<span class="_ _4"></span>yte</div><div class="t m1 x2 h7 y6d ff2 fs4 fc0 sc0 ls46 wsa5">command<span class="_ _1"></span> sequ<span class="_ _1"></span>ence w<span class="_ _1"></span>ith Er<span class="_ _1"></span>ase R<span class="_ _1"></span>esume co<span class="_ _1"></span>mmand <span class="_ _1"></span>(30H)</div><div class="t m1 x2 h7 yd1 ff2 fs4 fc0 sc0 ls36 ws48">at an<span class="_ _1"></span>y addres<span class="_ _1"></span>s in the last Byt<span class="_ _1"></span>e sequence<span class="_ _1"></span>.</div><div class="t m1 x2 h5 yd2 ff1 fs3 fc0 sc0 ls6a wsa6">Chip-Erase Oper<span class="_ _1"></span>ation</div><div class="t m1 x2 h7 yd3 ff2 fs4 fc0 sc0 ls6b wsa7">The SST39VF160x/320<span class="_ _1"></span>x/640x provide<span class="_ _1"></span> a Chip-Erase oper-</div><div class="t m1 x2 h7 yd4 ff2 fs4 fc0 sc0 ls6b wsa8">ation, which a<span class="_ _1"></span>llows the u<span class="_ _1"></span>ser to er<span class="_ _1"></span>ase the entir<span class="_ _1"></span>e memory</div><div class="t m1 x2 h7 yd5 ff2 fs4 fc0 sc0 ls6c wsa9">arra<span class="_ _4"></span>y to the “1” stat<span class="_ _1"></span>e. T<span class="_ _1"></span>his is useful when<span class="_ _1"></span> the entir<span class="_ _1"></span>e de<span class="_ _1"></span>vice</div><div class="t m1 x2 h7 yd6 ff2 fs4 fc0 sc0 ls6d wsaa">must be quic<span class="_ _1"></span>kly erased.</div><div class="t m1 x2 h7 yd7 ff2 fs4 fc0 sc0 ls2a wsab">The Chip-Erase o<span class="_ _1"></span>peration<span class="_ _1"></span> is initiated b<span class="_ _1"></span>y e<span class="_ _1"></span>x<span class="_ _1"></span>ecuting a six-</div><div class="t m1 x2 h7 yd8 ff2 fs4 fc0 sc0 ls28 wsac">by<span class="_ _1"></span>te command seque<span class="_ _1"></span>nce with Chip-<span class="_ _1"></span>Erase comma<span class="_ _1"></span>nd</div><div class="t m1 x2 h7 yd9 ff2 fs4 fc0 sc0 ls28 wsad">(10H) at address 5555<span class="_ _1"></span>H in the last b<span class="_ _1"></span>yte sequence<span class="_ _1"></span>. The</div><div class="t m1 x2 h7 yda ff2 fs4 fc0 sc0 ls4d ws4f">Erase op<span class="_ _1"></span>eration begins <span class="_ _1"></span>with the<span class="_ _1"></span> rising edge of the sixth</div><div class="t m1 x2 h7 ydb ff2 fs4 fc0 sc0 ls4d wsae">WE# or CE#, <span class="_ _1"></span>whiche<span class="_ _1"></span>v<span class="_ _1"></span>er occurs first.<span class="_ _1"></span> During the Erase</div><div class="t m1 x2 h7 ydc ff2 fs4 fc0 sc0 ls6d wsaf">operation,<span class="_ _1"></span> the only v<span class="_ _1"></span>alid read is T<span class="_ _3"></span>o<span class="_ _1"></span>ggle Bit or Data# P<span class="_ _4"></span>olling.</div><div class="t m1 x2 h7 ydd ff2 fs4 fc0 sc0 ls28 wsb0">See T<span class="_ _a"></span>abl<span class="_ _1"></span>e 6 f<span class="_ _1"></span>or the<span class="_ _1"></span> command sequence<span class="_ _1"></span>, Figure 9 <span class="_ _1"></span>f<span class="_ _1"></span>or tim-</div><div class="t m1 x2 h7 yde ff2 fs4 fc0 sc0 ls4d wsb1">ing diagr<span class="_ _1"></span>am, and Fig<span class="_ _1"></span>ure 23 f<span class="_ _1"></span>or the flo<span class="_ _1"></span>wchar<span class="_ _0"></span>t. Any com-</div><div class="t m1 x2 h7 ydf ff2 fs4 fc0 sc0 ls4d wsb2">mands issued during the C<span class="_ _1"></span>hip-Erase oper<span class="_ _1"></span>ation are</div><div class="t m1 x2 h7 ye0 ff2 fs4 fc0 sc0 ls2b wsb3">ignored. When WP# is lo<span class="_ _4"></span>w<span class="_ _1"></span>, any a<span class="_ _1"></span>ttempt to C<span class="_ _1"></span>hip-Erase will</div><div class="t m1 x2 h7 ye1 ff2 fs4 fc0 sc0 ls6e wsb4">be ignored<span class="_ _1"></span>. During the command seq<span class="_ _1"></span>uence, WP# sho<span class="_ _1"></span>uld</div><div class="t m1 x2 h7 ye2 ff2 fs4 fc0 sc0 ls37 wsb5">be statically held<span class="_ _1"></span> high or lo<span class="_ _1"></span>w<span class="_ _4"></span>.</div><div class="t m1 x2 h5 ye3 ff1 fs3 fc0 sc0 ls6f ws3">Write <span class="_ _1"></span>Operation Stat<span class="_ _1"></span>us Detect<span class="_ _1"></span>ion</div><div class="t m1 x2 h7 ye4 ff2 fs4 fc0 sc0 ls38 wsb6">The S<span class="_ _1"></span>ST39V<span class="_ _1"></span>F160<span class="_ _1"></span>x/32<span class="_ _1"></span>0x/64<span class="_ _1"></span>0x pro<span class="_ _4"></span>vide tw<span class="_ _1"></span>o sof<span class="_ _1"></span>tw<span class="_ _1"></span>are</div><div class="t m1 x2 h7 ye5 ff2 fs4 fc0 sc0 ls30 wsb7">means to<span class="_ _0"></span> detect th<span class="_ _0"></span>e compl<span class="_ _0"></span>etion of a<span class="_ _0"></span> Write<span class="_ _0"></span> (Program or</div><div class="t m1 x2 h7 ye6 ff2 fs4 fc0 sc0 ls34 wsb8">Erase) c<span class="_ _0"></span>ycle, in or<span class="_ _0"></span>der to op<span class="_ _0"></span>timize th<span class="_ _0"></span>e system<span class="_ _0"></span> writ<span class="_ _0"></span>e cycle</div><div class="t m1 x2 h7 ye7 ff2 fs4 fc0 sc0 ls5b wsb9">time. The so<span class="_ _0"></span>ftware detect<span class="_ _0"></span>ion inclu<span class="_ _0"></span>des two s<span class="_ _0"></span>tatus bits<span class="_ _0"></span>: Data#</div><div class="t m1 x2 h7 ye8 ff2 fs4 fc0 sc0 ls70 wsba">P<span class="_ _4"></span>o<span class="_ _0"></span>lling (<span class="_ _0"></span>DQ</div><div class="t m1 x1b h8 ye9 ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x1c h7 yea ff2 fs4 fc0 sc0 ls5c wsbb">) and T<span class="_ _3"></span>ogg<span class="_ _0"></span>le Bi<span class="_ _0"></span>t (DQ</div><div class="t m1 x1d h8 ye9 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x1e h7 yea ff2 fs4 fc0 sc0 ls5a wsbc">). The E<span class="_ _0"></span>nd-of-W<span class="_ _0"></span>rit<span class="_ _0"></span>e</div><div class="t m1 x2 h7 yeb ff2 fs4 fc0 sc0 ls34 wsb8">detecti<span class="_ _0"></span>on mode is enabled afte<span class="_ _0"></span>r the r<span class="_ _0"></span>ising edge of<span class="_ _0"></span> WE#,</div><div class="t m1 x2 h7 yec ff2 fs4 fc0 sc0 ls34 ws8">which i<span class="_ _0"></span>nitiates <span class="_ _0"></span>the inte<span class="_ _0"></span>rn<span class="_ _0"></span>al Program <span class="_ _0"></span>or Erase o<span class="_ _0"></span>peration.</div><div class="t m1 x2 h7 yed ff2 fs4 fc0 sc0 ls52 wsbd">The actual com<span class="_ _1"></span>pletion of<span class="_ _1"></span> the non<span class="_ _1"></span>v<span class="_ _1"></span>olatile<span class="_ _1"></span> write is asyn-</div><div class="t m1 x2 h7 yee ff2 fs4 fc0 sc0 ls71 wsbe">chronous w<span class="_ _1"></span>ith the syst<span class="_ _1"></span>em; theref<span class="_ _4"></span>ore, eit<span class="_ _1"></span>her a Data#<span class="_ _1"></span> P<span class="_ _4"></span>oll-</div><div class="t m1 x2 h7 yef ff2 fs4 fc0 sc0 ls56 wsbf">ing or<span class="_ _1"></span> T<span class="_ _a"></span>oggle Bit read<span class="_ _1"></span> ma<span class="_ _1"></span>y be <span class="_ _1"></span>simultan<span class="_ _1"></span>eous wi<span class="_ _1"></span>th the</div><div class="t m1 x2 h7 yf0 ff2 fs4 fc0 sc0 ls72 wsc0">completio<span class="_ _1"></span>n of the write cycle. If th<span class="_ _1"></span>is occurs, th<span class="_ _1"></span>e system</div><div class="t m1 x2 h7 yf1 ff2 fs4 fc0 sc0 ls73 ws12">may possi<span class="_ _0"></span>bly get a<span class="_ _0"></span>n err<span class="_ _0"></span>oneo<span class="_ _0"></span>us re<span class="_ _0"></span>sult,<span class="_ _0"></span> i.e.,<span class="_ _0"></span> valid data<span class="_ _0"></span> may</div><div class="t m1 x2 h7 yf2 ff2 fs4 fc0 sc0 ls74 ws24">appear<span class="_ _1"></span> to conf<span class="_ _1"></span>lict wit<span class="_ _1"></span>h eith<span class="_ _1"></span>er DQ</div><div class="t m1 x1f h8 yf3 ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x20 h7 yf4 ff2 fs4 fc0 sc0 ls75 wsc1"> or DQ</div><div class="t m1 x21 h8 yf3 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x22 h7 yf4 ff2 fs4 fc0 sc0 ls76 ws74">. In ord<span class="_ _0"></span>er to pre<span class="_ _0"></span>-</div><div class="t m1 x2 h7 yf5 ff2 fs4 fc0 sc0 ls52 wsc2">v<span class="_ _1"></span>ent spu<span class="_ _1"></span>rious rejectio<span class="_ _1"></span>n, if an <span class="_ _1"></span>erroneou<span class="_ _1"></span>s result <span class="_ _1"></span>occurs<span class="_ _1"></span>, the</div><div class="t m1 x2 h7 yf6 ff2 fs4 fc0 sc0 ls43 wsc3">softw<span class="_ _1"></span>are rout<span class="_ _1"></span>ine should include<span class="_ _1"></span> a loop to read the</div><div class="t m1 x2 h7 yf7 ff2 fs4 fc0 sc0 ls77 wsc4">acce<span class="_ _0"></span>ssed l<span class="_ _0"></span>ocat<span class="_ _0"></span>ion a<span class="_ _0"></span>n add<span class="_ _0"></span>ition<span class="_ _0"></span>al two (<span class="_ _0"></span>2) ti<span class="_ _0"></span>mes. If <span class="_ _0"></span>both</div><div class="t m1 x2 h7 yf8 ff2 fs4 fc0 sc0 ls54 wsc5">reads <span class="_ _1"></span>are v<span class="_ _4"></span>a<span class="_ _0"></span>lid,<span class="_ _1"></span> then t<span class="_ _1"></span>he de<span class="_ _4"></span>vice has compl<span class="_ _1"></span>eted the<span class="_ _1"></span> Write</div><div class="t m1 x2 h7 yf9 ff2 fs4 fc0 sc0 ls78 wsc6">cycle,<span class="_ _1"></span> otherwise t<span class="_ _1"></span>he rejectio<span class="_ _1"></span>n is v<span class="_ _1"></span>alid.</div><div class="t m1 x2 h5 yfa ff1 fs3 fc0 sc0 ls79 wsc7">Data# Polling (DQ</div><div class="t m1 x23 hb yfb ff1 fs6 fc0 sc0 ls3 ws2">7</div><div class="t m1 x24 h5 yfa ff1 fs3 fc0 sc0 ls3 ws2">)</div><div class="t m1 x2 h7 yfc ff2 fs4 fc0 sc0 ls38 wsc8">When the SST39VF<span class="_ _1"></span>160x/320x/640x ar<span class="_ _1"></span>e in the internal</div><div class="t m1 x2 h7 yfd ff2 fs4 fc0 sc0 ls73 wsc9">Progr<span class="_ _1"></span>am opera<span class="_ _1"></span>tion, any a<span class="_ _1"></span>ttempt t<span class="_ _1"></span>o read DQ</div><div class="t m1 x25 h8 yfe ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x26 h7 yff ff2 fs4 fc0 sc0 ls39 ws43"> will produce</div><div class="t m1 x2 h7 y100 ff2 fs4 fc0 sc0 ls3b ws37">the complement<span class="_ _1"></span> of the true <span class="_ _1"></span>data. Once <span class="_ _1"></span>the Progr<span class="_ _1"></span>am oper-</div><div class="t m1 x2 h7 y101 ff2 fs4 fc0 sc0 ls3b ws3b">ation is complete<span class="_ _1"></span>d, DQ</div><div class="t m1 x27 h8 y102 ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x23 h7 y103 ff2 fs4 fc0 sc0 ls6e wsca"> will produce<span class="_ _1"></span> true data.<span class="_ _1"></span> Note<span class="_ _1"></span> th<span class="_ _1"></span>at</div><div class="t m1 x2 h7 y104 ff2 fs4 fc0 sc0 ls7a wscb">ev<span class="_ _4"></span>en t<span class="_ _0"></span>hough DQ</div><div class="t m1 x28 h8 y105 ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x29 h7 y106 ff2 fs4 fc0 sc0 ls35 ws8c"> may hav<span class="_ _1"></span>e valid data<span class="_ _0"></span> imm<span class="_ _0"></span>ediately<span class="_ _0"></span> f<span class="_ _1"></span>ollow-</div><div class="t m1 xb h7 y107 ff2 fs4 fc0 sc0 ls32 wscc">ing the comp<span class="_ _0"></span>letion of an in<span class="_ _0"></span>ter<span class="_ _0"></span>nal Wr<span class="_ _0"></span>ite opera<span class="_ _0"></span>tion, the</div><div class="t m1 xb h7 y108 ff2 fs4 fc0 sc0 ls2d wscd">remain<span class="_ _0"></span>ing da<span class="_ _0"></span>ta outputs<span class="_ _0"></span> may still be invalid: valid da<span class="_ _0"></span>ta on th<span class="_ _0"></span>e</div><div class="t m1 xb h7 y109 ff2 fs4 fc0 sc0 ls31 wsce">entire<span class="_ _0"></span> data bus will app<span class="_ _0"></span>ear in subs<span class="_ _0"></span>equent s<span class="_ _0"></span>uccessi<span class="_ _0"></span>v<span class="_ _1"></span>e Rea<span class="_ _0"></span>d</div><div class="t m1 xb h7 y10a ff2 fs4 fc0 sc0 ls6e wscf">cycle<span class="_ _1"></span>s aft<span class="_ _1"></span>er an in<span class="_ _1"></span>terva<span class="_ _1"></span>l of <span class="_ _1"></span>1 µs.<span class="_ _1"></span> During internal Erase oper-</div><div class="t m1 xb h7 y10b ff2 fs4 fc0 sc0 ls27 ws22">ation, an<span class="_ _4"></span>y attempt to rea<span class="_ _1"></span>d DQ</div><div class="t m1 x2a h8 y10c ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x1a h7 y10d ff2 fs4 fc0 sc0 ls2b wsd0"> will produce a ‘0’. Once the</div><div class="t m1 xb h7 y10e ff2 fs4 fc0 sc0 ls6c wsd1">internal Erase operation is complet<span class="_ _1"></span>ed, DQ</div><div class="t m1 x2b h8 y10f ff2 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m1 x2c h7 y110 ff2 fs4 fc0 sc0 ls2b wsd2"> will produce a</div><div class="t m1 xb h7 y111 ff2 fs4 fc0 sc0 ls28 ws24">‘1’. The Dat<span class="_ _1"></span>a# P<span class="_ _4"></span>olling is valid afte<span class="_ _1"></span>r the rising edge of f<span class="_ _4"></span>our<span class="_ _0"></span>th</div><div class="t m1 xb h7 y112 ff2 fs4 fc0 sc0 ls4d wsd3">WE# (or CE#) pu<span class="_ _1"></span>lse fo<span class="_ _1"></span>r Progr<span class="_ _1"></span>am operation.<span class="_ _1"></span> F<span class="_ _1"></span>or Sector-,</div><div class="t m1 xb h7 y113 ff2 fs4 fc0 sc0 ls4d wsd4">Bloc<span class="_ _1"></span>k- or Chip-Er<span class="_ _1"></span>ase, th<span class="_ _1"></span>e Data# P<span class="_ _4"></span>olling is v<span class="_ _4"></span>alid after the</div><div class="t m1 xb h7 y114 ff2 fs4 fc0 sc0 ls4d wsd5">rising edge of sixt<span class="_ _1"></span>h WE# (or CE#) pu<span class="_ _1"></span>lse. <span class="_ _1"></span>See Figure 6 f<span class="_ _4"></span>or</div><div class="t m1 xb h7 y115 ff2 fs4 fc0 sc0 ls28 wsd6">Data# P<span class="_ _4"></span>olling timing diag<span class="_ _1"></span>ram an<span class="_ _1"></span>d Figure 20 f<span class="_ _4"></span>or a flowchar<span class="_ _0"></span>t.</div><div class="t m1 xb h5 y116 ff1 fs3 fc0 sc0 ls7b wsd7">Toggle Bits (D<span class="ls7c wsd8">Q6 and DQ2)</span></div><div class="t m1 xb h7 y117 ff2 fs4 fc0 sc0 ls2e wsd9">Duri<span class="_ _0"></span>ng the inte<span class="_ _0"></span>r<span class="_ _0"></span>nal Program or Era<span class="_ _0"></span>se operation<span class="_ _0"></span>, any con-</div><div class="t m1 xb h7 y118 ff2 fs4 fc0 sc0 ls7d wsda">secutive attempts to read<span class="_ _0"></span> DQ</div><div class="t m1 x2d h8 y119 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x2e h7 y11a ff2 fs4 fc0 sc0 ls28 wsdb"> wil<span class="_ _1"></span>l prod<span class="_ _1"></span>uce alt<span class="_ _1"></span>ernatin<span class="_ _1"></span>g “1”s</div><div class="t m1 xb h7 y11b ff2 fs4 fc0 sc0 ls45 wsdc">and “0”s, i.e., togg<span class="_ _0"></span>ling between<span class="_ _0"></span> 1 and 0. When<span class="_ _0"></span> the inte<span class="_ _0"></span>rnal</div><div class="t m1 xb h7 y11c ff2 fs4 fc0 sc0 ls45 wsdd">Program or<span class="_ _0"></span> Erase op<span class="_ _0"></span>eration i<span class="_ _0"></span>s compl<span class="_ _0"></span>eted, the<span class="_ _0"></span> DQ</div><div class="t m1 x2f h8 y11d ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x30 h7 y11e ff2 fs4 fc0 sc0 ls7e wsde"> bit w<span class="_ _1"></span>ill</div><div class="t m1 xb h7 y11f ff2 fs4 fc0 sc0 ls2b ws9d">stop t<span class="_ _1"></span>oggli<span class="_ _1"></span>ng. Th<span class="_ _1"></span>e de<span class="_ _1"></span>vice i<span class="_ _1"></span>s then<span class="_ _1"></span> ready f<span class="_ _4"></span>or the ne<span class="_ _4"></span>xt opera<span class="_ _1"></span>-</div><div class="t m1 xb h7 y120 ff2 fs4 fc0 sc0 ls34 ws23">tion. For Sect<span class="_ _0"></span>or-, Blo<span class="_ _0"></span>ck<span class="_ _1"></span>-, or<span class="_ _0"></span> Chip-Eras<span class="_ _0"></span>e, the toggl<span class="_ _0"></span>e bit (DQ</div><div class="t m1 x31 h8 y121 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x32 h7 y122 ff2 fs4 fc0 sc0 ls3 ws2">)</div><div class="t m1 xb h7 y123 ff2 fs4 fc0 sc0 ls30 wsdf">is valid after<span class="_ _0"></span> the ri<span class="_ _0"></span>sing ed<span class="_ _0"></span>ge of six<span class="_ _0"></span>th WE# (or<span class="_ _0"></span> CE#) pul<span class="_ _0"></span>se.</div><div class="t m1 xb h7 y124 ff2 fs4 fc0 sc0 ls64 ws2">DQ</div><div class="t m1 x17 h8 y125 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x18 h7 y126 ff2 fs4 fc0 sc0 ls59 wsd6"> will<span class="_ _0"></span> be se<span class="_ _0"></span>t to “1<span class="_ _0"></span>” if a<span class="_ _0"></span> Read <span class="_ _0"></span>operatio<span class="_ _0"></span>n is a<span class="_ _0"></span>ttempted <span class="_ _0"></span>on a<span class="_ _0"></span>n</div><div class="t m1 xb h7 y127 ff2 fs4 fc0 sc0 ls35 wse0">Erase-Su<span class="_ _0"></span>spen<span class="_ _0"></span>ded Sec<span class="_ _0"></span>tor/Bl<span class="_ _0"></span>ock. If Program <span class="_ _0"></span>operation i<span class="_ _0"></span>s ini-</div><div class="t m1 xb h7 y128 ff2 fs4 fc0 sc0 ls5e wse1">tiat<span class="_ _1"></span>ed in a sec<span class="_ _1"></span>tor/b<span class="_ _4"></span>lock<span class="_ _1"></span> not sele<span class="_ _1"></span>cted in Er<span class="_ _4"></span>ase-Suspe<span class="_ _1"></span>nd</div><div class="t m1 xb h7 y129 ff2 fs4 fc0 sc0 ls7d wse2">mode, DQ</div><div class="t m1 x33 h8 y12a ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x34 h7 y12b ff2 fs4 fc0 sc0 ls6d wse3"> will<span class="_ _1"></span> togg<span class="_ _1"></span>le<span class="_ _1"></span>.</div><div class="t m1 xb h7 y12c ff2 fs4 fc0 sc0 ls2e wse4">An addi<span class="_ _0"></span>tiona<span class="_ _0"></span>l T<span class="_ _a"></span>o<span class="_ _0"></span>ggle Bit i<span class="_ _0"></span>s av<span class="_ _1"></span>ailable on DQ</div><div class="t m1 x2b h8 y12d ff2 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m1 x2c h7 y12e ff2 fs4 fc0 sc0 ls7f wse5">, whi<span class="_ _1"></span>ch c<span class="_ _1"></span>an be</div><div class="t m1 xb h7 y12f ff2 fs4 fc0 sc0 ls59 wse6">used in c<span class="_ _0"></span>onjunct<span class="_ _0"></span>ion with DQ</div><div class="t m1 x1 h8 y130 ff2 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m1 x35 h7 y131 ff2 fs4 fc0 sc0 ls6c wse7"> to ch<span class="_ _1"></span>ec<span class="_ _1"></span>k wh<span class="_ _1"></span>ether<span class="_ _1"></span> a pa<span class="_ _1"></span>r<span class="_ _0"></span>ticula<span class="_ _1"></span>r</div><div class="t m1 xb h7 y132 ff2 fs4 fc0 sc0 ls46 wse8">sector<span class="_ _0"></span> is be<span class="_ _0"></span>ing act<span class="_ _0"></span>ively erased o<span class="_ _0"></span>r erase<span class="_ _0"></span>-susp<span class="_ _0"></span>ended. T<span class="_ _3"></span>a<span class="_ _0"></span>b<span class="_ _1"></span>le 1</div><div class="t m1 xb h7 y133 ff2 fs4 fc0 sc0 ls37 wse9">sho<span class="_ _1"></span>ws det<span class="_ _1"></span>aile<span class="_ _1"></span>d statu<span class="_ _1"></span>s bits<span class="_ _1"></span> inf<span class="_ _4"></span>or<span class="_ _0"></span>mati<span class="_ _1"></span>on. The T<span class="_ _a"></span>ogg<span class="_ _1"></span>le Bit</div><div class="t m1 xb h7 y134 ff2 fs4 fc0 sc0 ls80 ws2">(DQ</div><div class="t m1 x36 h8 y135 ff2 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m1 x37 h7 y136 ff2 fs4 fc0 sc0 ls30 ws9">) is valid <span class="_ _0"></span>after the r<span class="_ _0"></span>is<span class="_ _0"></span>ing edge o<span class="_ _0"></span>f the l<span class="_ _0"></span>ast WE# <span class="_ _0"></span>(or CE#)</div><div class="t m1 xb h7 y137 ff2 fs4 fc0 sc0 ls35 wsea">pulse of Wr<span class="_ _0"></span>ite op<span class="_ _0"></span>eration. Se<span class="_ _0"></span>e Figure 7 for T<span class="_ _a"></span>oggl<span class="_ _0"></span>e Bit timin<span class="_ _0"></span>g</div><div class="t m1 xb h7 y138 ff2 fs4 fc0 sc0 ls2f ws1d">diagram an<span class="_ _0"></span>d Figure 20<span class="_ _0"></span> for a flowchar<span class="_ _0"></span>t.</div><div class="t m1 xb hc y139 ff1 fs8 fc0 sc0 ls81 ws2">Note:<span class="_ _b"> </span><span class="ff2 ls82">DQ</span></div><div class="t m1 x38 h3 y13a ff2 fs1 fc0 sc0 ls3 ws2">7</div><div class="t m1 x39 hd y139 ff2 fs8 fc0 sc0 ls83 wseb"> and DQ</div><div class="t m1 x3a h3 y13a ff2 fs1 fc0 sc0 ls3 ws2">2</div><div class="t m1 x3b hd y139 ff2 fs8 fc0 sc0 ls84 wsec"> require a v<span class="_ _1"></span>alid address when reading</div><div class="t m1 x3c hd y13b ff2 fs8 fc0 sc0 ls85 wsed">status inf<span class="_ _1"></span>or<span class="_ _0"></span>mation.</div><div class="t m1 xb h6 y13c ff1 fs4 fc0 sc0 ls86 ws2">T<span class="_ _3"></span>ABLE<span class="_ _5"> </span>1:<span class="_ _c"> </span>W<span class="fs8 ls87">RITE</span><span class="ls88"> O<span class="fs8 ls89">PERATI<span class="_ _1"></span>ON<span class="fs4 ls88"> S</span><span class="ls8a">TATUS</span></span></span></div><div class="t m1 x3d hb y13d ff1 fs6 fc0 sc0 ls8b ws2">Status<span class="_ _d"> </span>DQ</div><div class="t m1 x3e he y13e ff1 fs9 fc0 sc0 ls3 ws2">7</div><div class="t m1 x3f hb y13d ff1 fs6 fc0 sc0 ls8c ws2">DQ</div><div class="t m1 x40 he y13e ff1 fs9 fc0 sc0 ls3 ws2">6</div><div class="t m1 x41 hb y13d ff1 fs6 fc0 sc0 ls8c ws2">DQ</div><div class="t m1 x42 he y13e ff1 fs9 fc0 sc0 ls3 ws2">2</div><div class="t m1 x3d hd y13f ff2 fs8 fc0 sc0 ls83 ws2">Norm<span class="_ _0"></span>al </div><div class="t m1 x3d hd y140 ff2 fs8 fc0 sc0 ls8d ws2">Operation</div><div class="t m1 x34 hd y13f ff2 fs8 fc0 sc0 ls8d ws2">Standard </div><div class="t m1 x34 hd y140 ff2 fs8 fc0 sc0 ls8e ws2">Prog<span class="_ _1"></span>ra<span class="_ _1"></span>m</div><div class="t m1 x43 hd y13f ff2 fs8 fc0 sc0 ls82 ws2">DQ</div><div class="t m1 x44 h3 y141 ff2 fs1 fc0 sc0 ls3 ws2">7</div><div class="t m1 x3e hd y13f ff2 fs8 fc0 sc0 ls8f wsee">#<span class="_ _e"> </span>T<span class="_ _3"></span>oggle<span class="_ _e"> </span>No T<span class="_ _4"></span>oggle</div><div class="t m1 x34 hd y142 ff2 fs8 fc0 sc0 ls85 ws2">Standard </div><div class="t m1 x34 hd y143 ff2 fs8 fc0 sc0 ls8e ws2">Era<span class="_ _1"></span>se</div><div class="t m1 x45 hd y142 ff2 fs8 fc0 sc0 ls8f ws2">0<span class="_ _f"> </span>T<span class="_ _3"></span>oggle<span class="_ _10"> </span>T<span class="_ _3"></span>oggle</div><div class="t m1 x3d hd y144 ff2 fs8 fc0 sc0 ls90 ws2">Erase-</div><div class="t m1 x3d hd y145 ff2 fs8 fc0 sc0 ls84 wsec">Suspend </div><div class="t m1 x3d hd y146 ff2 fs8 fc0 sc0 ls91 ws2">Mode</div><div class="t m1 x34 hd y147 ff2 fs8 fc0 sc0 ls8d wsef">Read from </div><div class="t m1 x34 hd y148 ff2 fs8 fc0 sc0 ls92 ws2">Erase-Suspended</div><div class="t m1 x34 hd y149 ff2 fs8 fc0 sc0 ls93 ws2">Sector/Block </div><div class="t m1 x45 hd y14a ff2 fs8 fc0 sc0 ls83 ws2">1<span class="_ _11"> </span>1<span class="_ _12"> </span>T<span class="_ _3"></span>oggle</div><div class="t m1 x34 hd y14b ff2 fs8 fc0 sc0 ls8f wsf0">Read from</div><div class="t m1 x34 hd y14c ff2 fs8 fc0 sc0 ls94 wsf1">Non- Erase-Suspended</div><div class="t m1 x34 hd y14d ff2 fs8 fc0 sc0 ls8e ws2">Sect<span class="_ _1"></span>or/<span class="_ _1"></span>Bloc<span class="_ _4"></span>k</div><div class="t m1 x46 hd y14e ff2 fs8 fc0 sc0 ls95 ws2">Data<span class="_ _13"> </span>Data<span class="_ _14"> </span>Data</div><div class="t m1 x34 hd y14f ff2 fs8 fc0 sc0 ls8e ws2">Prog<span class="_ _1"></span>ra<span class="_ _1"></span>m<span class="_ _15"> </span>DQ</div><div class="t m1 x44 h3 y150 ff2 fs1 fc0 sc0 ls3 ws2">7</div><div class="t m1 x3e hd y151 ff2 fs8 fc0 sc0 ls91 ws2">#<span class="_ _e"> </span>T<span class="_ _3"></span>oggle<span class="_ _16"> </span>N/A</div><div class="t m1 x41 h3 y152 ff2 fs1 fc0 sc0 ls96 ws2">T1.0<span class="_ _17"> </span>1223</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg4.jpg"><div class="t m2 x10 h9 y66 ff2 fs6 fc0 sc0 ls3 ws2">4</div><div class="t m2 x2 h7 y1 ff2 fs4 fc0 sc0 ls3e ws4a">Prelim<span class="_ _0"></span>inary S<span class="_ _0"></span>peci<span class="_ _0"></span>fication<span class="_ _0"></span>s</div><div class="t m2 x11 ha y67 ff1 fs7 fc0 sc0 ls3f ws4b">16 Mbit / 32 Mbit / 64<span class="_ _0"></span> Mbit Multi-Purpose<span class="_ _0"></span> Flash Plus</div><div class="t m2 x12 ha y68 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1601 / SST<span class="_ _0"></span>39VF3201 / SS<span class="_ _0"></span>T39VF6401</div><div class="t m2 x12 ha y69 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1602 / SST<span class="_ _0"></span>39VF3202 / SS<span class="_ _0"></span>T39VF6402</div><div class="t m2 x2 h3 y2 ff2 fs1 fc0 sc0 ls41 ws4d">©<span class="_ _0"></span>2003 Silicon Sto<span class="_ _0"></span>rage Technology, Inc.<span class="_ _7"> </span><span class="ls2 ws2">S71223-03<span class="_ _1"></span>-000<span class="_ _8"> </span>11/03</span></div><div class="t m2 x2 h5 y153 ff1 fs3 fc0 sc0 ls79 wsc7">Data Protection</div><div class="t m2 x2 h7 y154 ff2 fs4 fc0 sc0 ls2d wsf2">The SST39<span class="_ _1"></span>VF160x/<span class="_ _1"></span>320x/64<span class="_ _1"></span>0x provi<span class="_ _1"></span>de bot<span class="_ _1"></span>h hardw<span class="_ _1"></span>are and</div><div class="t m2 x2 h7 y155 ff2 fs4 fc0 sc0 ls97 ws9">softwar<span class="_ _0"></span>e f<span class="_ _1"></span>eat<span class="_ _0"></span>ures to<span class="_ _0"></span> prot<span class="_ _0"></span>ect no<span class="_ _0"></span>nv<span class="_ _4"></span>o<span class="_ _0"></span>latil<span class="_ _0"></span>e data<span class="_ _0"></span> from<span class="_ _0"></span> inadver<span class="_ _9"></span>tent</div><div class="t m2 x2 h7 y156 ff2 fs4 fc0 sc0 ls98 ws2">writ<span class="_ _0"></span>es.</div><div class="t m2 x2 h5 y157 ff1 fs3 fc0 sc0 ls99 wsf3">Hardware Data Protection</div><div class="t m2 x2 h7 y158 ff2 fs4 fc0 sc0 ls46 ws51">Noise/G<span class="_ _0"></span>litch<span class="_ _0"></span> Prote<span class="_ _0"></span>ction:<span class="_ _0"></span><span class="ls6c"> A WE# o<span class="_ _1"></span>r CE<span class="_ _1"></span># puls<span class="_ _1"></span>e of<span class="_ _1"></span> less t<span class="_ _1"></span>han 5</span></div><div class="t m2 x2 h7 y159 ff2 fs4 fc0 sc0 ls9a wsf4">ns will<span class="_ _1"></span> not ini<span class="_ _1"></span>tiate<span class="_ _1"></span> a write cycl<span class="_ _1"></span>e.</div><div class="t m2 x2 h7 y15a ff2 fs4 fc0 sc0 ls3 ws2">V</div><div class="t m2 x47 h8 y15b ff2 fs5 fc0 sc0 ls49 ws2">DD</div><div class="t m2 x48 h7 y15c ff2 fs4 fc0 sc0 ls9b wsf5"> P<span class="_ _4"></span>ower Up/Down D<span class="_ _0"></span>etection:<span class="ls2d wsf6"> The Wr<span class="_ _0"></span>ite<span class="_ _0"></span> operatio<span class="_ _0"></span>n is</span></div><div class="t m2 x2 h7 y15d ff2 fs4 fc0 sc0 ls45 ws8b">inhibi<span class="_ _0"></span>ted when <span class="_ _0"></span>V</div><div class="t m2 x49 h8 y15e ff2 fs5 fc0 sc0 ls49 ws2">DD</div><div class="t m2 xf h7 y15f ff2 fs4 fc0 sc0 ls5c ws6e"> is le<span class="_ _0"></span>ss than<span class="_ _0"></span> 1.5V<span class="_ _3"></span>.</div><div class="t m2 x2 h7 y160 ff2 fs4 fc0 sc0 ls59 wsf7">Wr<span class="_ _0"></span>ite Inhi<span class="_ _0"></span>bit Mo<span class="_ _0"></span>de:</div><div class="t m2 x4a h7 y161 ff2 fs4 fc0 sc0 ls58 wsf8"> F<span class="_ _1"></span>orcing<span class="_ _0"></span> OE# low<span class="_ _4"></span>, CE#<span class="_ _0"></span> high, or<span class="_ _0"></span> WE#</div><div class="t m2 x2 h7 y162 ff2 fs4 fc0 sc0 ls31 wsf9">high will<span class="_ _0"></span> inhibi<span class="_ _0"></span>t the Writ<span class="_ _0"></span>e operation<span class="_ _0"></span>. This prevents inadver<span class="_ _0"></span>t-</div><div class="t m2 x2 h7 y163 ff2 fs4 fc0 sc0 ls4d ws65">ent w<span class="_ _1"></span>rites du<span class="_ _1"></span>ring po<span class="_ _1"></span>wer<span class="_ _1"></span>-up or<span class="_ _1"></span> pow<span class="_ _4"></span>er-dow<span class="_ _1"></span>n.</div><div class="t m2 x2 h5 y164 ff1 fs3 fc0 sc0 ls7c wsfa">Hardware Bloc<span class="ls9c wsfb">k Protecti<span class="_ _0"></span>on</span></div><div class="t m2 x2 h7 y165 ff2 fs4 fc0 sc0 ls5a wsfc">The S<span class="_ _0"></span>ST39VF160<span class="_ _0"></span>2/3202/6<span class="_ _0"></span>402 sup<span class="_ _0"></span>por<span class="_ _0"></span>t to<span class="_ _0"></span>p hard<span class="_ _0"></span>ware bloc<span class="_ _1"></span>k</div><div class="t m2 x2 h7 y166 ff2 fs4 fc0 sc0 ls34 wsfd">protec<span class="_ _0"></span>tion, whi<span class="_ _0"></span>ch protec<span class="_ _0"></span>ts the top 3<span class="_ _0"></span>2 KWord bl<span class="_ _1"></span>ock of the</div><div class="t m2 x2 h7 y167 ff2 fs4 fc0 sc0 ls34 ws9b">device. The SST39VF16<span class="_ _0"></span>01/32<span class="_ _0"></span>01/6401 su<span class="_ _0"></span>ppor<span class="_ _0"></span>t bo<span class="_ _0"></span>ttom</div><div class="t m2 x2 h7 y168 ff2 fs4 fc0 sc0 ls7f wsb8">har<span class="_ _1"></span>dwa<span class="_ _1"></span>re b<span class="_ _1"></span>loc<span class="_ _4"></span>k protec<span class="_ _1"></span>tion,<span class="_ _1"></span> whic<span class="_ _1"></span>h prot<span class="_ _1"></span>ects<span class="_ _1"></span> the bot<span class="_ _1"></span>tom 32</div><div class="t m2 x2 h7 y169 ff2 fs4 fc0 sc0 ls59 ws24">KWord block of the device. The B<span class="_ _0"></span>oot B<span class="_ _0"></span>lock addres<span class="_ _0"></span>s ranges</div><div class="t m2 x2 h7 y16a ff2 fs4 fc0 sc0 ls59 wsfe">are de<span class="_ _0"></span>scr<span class="_ _0"></span>ibed in <span class="_ _0"></span>T<span class="_ _3"></span>able 2. Program <span class="_ _0"></span>and Era<span class="_ _0"></span>se operatio<span class="_ _0"></span>ns</div><div class="t m2 x2 h7 y16b ff2 fs4 fc0 sc0 ls2c wsff">are prevented on th<span class="_ _0"></span>e 32 <span class="_ _0"></span>KW<span class="_ _1"></span>ord w<span class="_ _0"></span>hen WP<span class="_ _0"></span># is low<span class="_ _4"></span>. <span class="_ _0"></span>If WP# <span class="_ _0"></span>is</div><div class="t m2 x2 h7 y16c ff2 fs4 fc0 sc0 ls5c ws100">left f<span class="_ _0"></span>loating<span class="_ _0"></span>, it is i<span class="_ _0"></span>nter<span class="_ _0"></span>nall<span class="_ _0"></span>y held h<span class="_ _0"></span>igh via a <span class="_ _0"></span>pull-u<span class="_ _0"></span>p resi<span class="_ _0"></span>stor<span class="_ _1"></span>,</div><div class="t m2 x2 h7 y16d ff2 fs4 fc0 sc0 ls2e ws3b">and the B<span class="_ _0"></span>oot Block is <span class="_ _0"></span>unprote<span class="_ _0"></span>cted, ena<span class="_ _0"></span>bling Program an<span class="_ _0"></span>d</div><div class="t m2 x2 h7 y16e ff2 fs4 fc0 sc0 ls59 ws24">Erase o<span class="_ _0"></span>perations o<span class="_ _0"></span>n that<span class="_ _0"></span> block.</div><div class="t m2 xb h5 y153 ff1 fs3 fc0 sc0 ls9d ws101">Hardware Reset (RST#)</div><div class="t m2 xb h7 y154 ff2 fs4 fc0 sc0 ls5a ws16">The RS<span class="_ _0"></span>T# pin provid<span class="_ _0"></span>es a hard<span class="_ _0"></span>ware method<span class="_ _0"></span> of res<span class="_ _0"></span>etting th<span class="_ _0"></span>e</div><div class="t m2 xb h7 y155 ff2 fs4 fc0 sc0 ls9e ws102">de<span class="_ _4"></span>vice to read<span class="_ _1"></span> arra<span class="_ _4"></span>y data.<span class="_ _1"></span> When t<span class="_ _1"></span>he RST#<span class="_ _1"></span> pin i<span class="_ _1"></span>s held lo<span class="_ _1"></span>w</div><div class="t m2 xb h7 y156 ff2 fs4 fc0 sc0 ls4a ws103">f<span class="_ _1"></span>or at leas<span class="_ _0"></span>t T</div><div class="t m2 x4b h8 y16f ff2 fs5 fc0 sc0 ls49 ws2">RP<span class="_ _a"></span>,</div><div class="t m2 x4c h7 y170 ff2 fs4 fc0 sc0 ls35 wse0"> any in-pr<span class="_ _0"></span>ogress opera<span class="_ _0"></span>tion will<span class="_ _0"></span> ter<span class="_ _0"></span>minate<span class="_ _0"></span> and</div><div class="t m2 xb h7 y171 ff2 fs4 fc0 sc0 ls37 ws104">ret<span class="_ _1"></span>ur<span class="_ _0"></span>n t<span class="_ _1"></span>o Read mo<span class="_ _1"></span>de<span class="_ _1"></span>. When<span class="_ _1"></span> no int<span class="_ _1"></span>ernal Prog<span class="_ _1"></span>ram/<span class="_ _1"></span>Er<span class="_ _1"></span>ase</div><div class="t m2 xb h7 y172 ff2 fs4 fc0 sc0 ls33 ws105">operatio<span class="_ _0"></span>n is in p<span class="_ _0"></span>rogress, a mi<span class="_ _0"></span>nimum pe<span class="_ _0"></span>riod o<span class="_ _0"></span>f T</div><div class="t m2 x4d h8 y173 ff2 fs5 fc0 sc0 ls49 ws2">RHR</div><div class="t m2 x4e h7 y174 ff2 fs4 fc0 sc0 ls9f ws106"> is</div><div class="t m2 xb h7 y175 ff2 fs4 fc0 sc0 ls31 wsa0">requir<span class="_ _0"></span>ed after<span class="_ _0"></span> RST# is d<span class="_ _0"></span>riven high b<span class="_ _0"></span>ef<span class="_ _1"></span>ore a<span class="_ _0"></span> v<span class="_ _1"></span>alid Re<span class="_ _0"></span>ad can</div><div class="t m2 xb h7 y176 ff2 fs4 fc0 sc0 ls2f ws1d">take place (<span class="_ _0"></span>see Figu<span class="_ _0"></span>re 15).</div><div class="t m2 xb h7 y177 ff2 fs4 fc0 sc0 ls2e ws107">The Erase<span class="_ _0"></span> or Program o<span class="_ _0"></span>peration t<span class="_ _0"></span>hat has be<span class="_ _0"></span>en inter<span class="_ _0"></span>rupte<span class="_ _0"></span>d</div><div class="t m2 xb h7 y178 ff2 fs4 fc0 sc0 ls32 ws108">needs t<span class="_ _0"></span>o be re<span class="_ _0"></span>initiat<span class="_ _0"></span>ed aft<span class="_ _0"></span>er the <span class="_ _0"></span>de<span class="_ _1"></span>vice <span class="_ _0"></span>resumes <span class="_ _0"></span>nor<span class="_ _0"></span>mal</div><div class="t m2 xb h7 y179 ff2 fs4 fc0 sc0 ls2c ws13">operatio<span class="_ _0"></span>n mode to<span class="_ _0"></span> ensu<span class="_ _0"></span>re data<span class="_ _0"></span> integri<span class="_ _0"></span>ty<span class="_ _3"></span>.</div><div class="t m2 xb h5 y17a ff1 fs3 fc0 sc0 lsa0 ws109">Software Data Protection (SDP)</div><div class="t m2 xb h7 y11a ff2 fs4 fc0 sc0 ls32 ws10a">The SS<span class="_ _0"></span>T39VF1<span class="_ _0"></span>60x/320<span class="_ _0"></span>x/640<span class="_ _0"></span>x provide t<span class="_ _0"></span>he JEDE<span class="_ _0"></span>C</div><div class="t m2 xb h7 y11b ff2 fs4 fc0 sc0 ls32 ws39">approved Software <span class="_ _0"></span>Data Pro<span class="_ _0"></span>tection<span class="_ _0"></span> scheme<span class="_ _0"></span> f<span class="_ _1"></span>or all <span class="_ _0"></span>data</div><div class="t m2 xb h7 y11c ff2 fs4 fc0 sc0 ls2e ws3c">alteration op<span class="_ _0"></span>erations, i.e.<span class="_ _0"></span>, Program and Erase. Any Pro-</div><div class="t m2 xb h7 y17b ff2 fs4 fc0 sc0 ls2e ws10b">gram operatio<span class="_ _0"></span>n require<span class="_ _0"></span>s the inc<span class="_ _0"></span>lusion of th<span class="_ _0"></span>e three-byte</div><div class="t m2 xb h7 y17c ff2 fs4 fc0 sc0 ls5c ws10c">sequ<span class="_ _0"></span>ence. The thr<span class="_ _0"></span>ee-byte lo<span class="_ _0"></span>ad seque<span class="_ _0"></span>nce is<span class="_ _0"></span> used to <span class="_ _0"></span>initiat<span class="_ _0"></span>e</div><div class="t m2 xb h7 y17d ff2 fs4 fc0 sc0 ls34 ws7d">the Pr<span class="_ _0"></span>ogram operation<span class="_ _0"></span>, providing<span class="_ _0"></span> optimal<span class="_ _0"></span> protecti<span class="_ _0"></span>on from</div><div class="t m2 xb h7 y17e ff2 fs4 fc0 sc0 ls32 ws10d">inadver<span class="_ _0"></span>ten<span class="_ _0"></span>t Wr<span class="_ _0"></span>ite op<span class="_ _0"></span>erations, e.g.<span class="_ _0"></span>, dur<span class="_ _0"></span>ing th<span class="_ _0"></span>e sys<span class="_ _0"></span>tem</div><div class="t m2 xb h7 y17f ff2 fs4 fc0 sc0 ls58 ws10e">power-up or p<span class="_ _0"></span>ow<span class="_ _1"></span>er-down. A<span class="_ _0"></span>ny Erase ope<span class="_ _0"></span>ration requi<span class="_ _0"></span>res the</div><div class="t m2 xb h7 y180 ff2 fs4 fc0 sc0 lsa1 ws10f">inclu<span class="_ _1"></span>sion of<span class="_ _1"></span> six-b<span class="_ _1"></span>yte se<span class="_ _1"></span>quenc<span class="_ _1"></span>e. Th<span class="_ _1"></span>ese de<span class="_ _4"></span>vices are s<span class="_ _1"></span>hipped</div><div class="t m2 xb h7 y181 ff2 fs4 fc0 sc0 ls7a ws110">with the So<span class="_ _0"></span>ftware Data Prote<span class="_ _0"></span>ction per<span class="_ _0"></span>mane<span class="_ _0"></span>ntly enabled.</div><div class="t m2 xb h7 y182 ff2 fs4 fc0 sc0 ls31 ws22">See T<span class="_ _3"></span>able 6 f<span class="_ _1"></span>or the spe<span class="_ _0"></span>cific soft<span class="_ _0"></span>ware comman<span class="_ _0"></span>d codes. Dur-</div><div class="t m2 xb h7 y183 ff2 fs4 fc0 sc0 ls59 wse6">ing SD<span class="_ _0"></span>P comman<span class="_ _0"></span>d seq<span class="_ _0"></span>uence, inv<span class="_ _1"></span>ali<span class="_ _0"></span>d comma<span class="_ _0"></span>nds wil<span class="_ _0"></span>l abor<span class="_ _9"></span>t</div><div class="t m2 xb h7 y184 ff2 fs4 fc0 sc0 ls4d ws111">the <span class="_ _1"></span>de<span class="_ _1"></span>vice<span class="_ _1"></span> to<span class="_ _1"></span> read <span class="_ _1"></span>mode w<span class="_ _1"></span>ith<span class="_ _1"></span>in T</div><div class="t m2 x4f h8 y185 ff2 fs5 fc0 sc0 ls49 ws2">RC.</div><div class="t m2 x50 h7 y186 ff2 fs4 fc0 sc0 ls34 ws112"> The conte<span class="_ _0"></span>nts of DQ</div><div class="t m2 x51 h8 y185 ff2 fs5 fc0 sc0 lsa2 ws2">15</div><div class="t m2 x32 h7 y186 ff2 fs4 fc0 sc0 ls3 ws2">-</div><div class="t m2 xb h7 y187 ff2 fs4 fc0 sc0 ls64 ws2">DQ</div><div class="t m2 x17 h8 y188 ff2 fs5 fc0 sc0 ls3 ws2">8</div><div class="t m2 x18 h7 y189 ff2 fs4 fc0 sc0 lsa3 ws113"> ca<span class="_ _0"></span>n be V</div><div class="t m2 x52 h8 y188 ff2 fs5 fc0 sc0 lsa4 ws2">IL</div><div class="t m2 x53 h7 y189 ff2 fs4 fc0 sc0 ls34 ws112"> or V</div><div class="t m2 x54 h8 y188 ff2 fs5 fc0 sc0 lsa4 ws2">IH</div><div class="t m2 x55 h7 y189 ff2 fs4 fc0 sc0 ls45 ws114">, but no oth<span class="_ _0"></span>er value, during<span class="_ _0"></span> any SDP</div><div class="t m2 xb h7 y18a ff2 fs4 fc0 sc0 ls46 wsa2">comm<span class="_ _0"></span>and seq<span class="_ _0"></span>uence.</div><div class="t m2 xb h5 y18b ff1 fs3 fc0 sc0 lsa5 ws115">Common Flash Memory Interface (CFI)</div><div class="t m2 xb h7 y18c ff2 fs4 fc0 sc0 ls28 ws78">The SST39VF160x/320x/640x also contain the CF<span class="_ _1"></span>I inf<span class="_ _1"></span>or-</div><div class="t m2 xb h7 y18d ff2 fs4 fc0 sc0 ls6c ws116">mation to describe the char<span class="_ _1"></span>acteristics of the de<span class="_ _1"></span>vice. In</div><div class="t m2 xb h7 y18e ff2 fs4 fc0 sc0 ls73 ws13">order to enter the C<span class="_ _1"></span>FI Quer<span class="_ _0"></span>y mode, the system must write</div><div class="t m2 xb h7 y18f ff2 fs4 fc0 sc0 ls27 ws22">three-b<span class="_ _1"></span>yte sequence, same as product ID entry command</div><div class="t m2 xb h7 y190 ff2 fs4 fc0 sc0 ls27 wsf9">with 98H (CFI Query command) to address 5555H in the</div><div class="t m2 xb h7 y191 ff2 fs4 fc0 sc0 ls4d ws65">last by<span class="_ _1"></span>te sequence. Once the de<span class="_ _4"></span>vic<span class="_ _0"></span>e enters the CFI Query</div><div class="t m2 xb h7 y192 ff2 fs4 fc0 sc0 ls3b ws117">mode, the system can re<span class="_ _1"></span>ad CFI data at the addresses</div><div class="t m2 xb h7 y193 ff2 fs4 fc0 sc0 ls28 ws118">giv<span class="_ _1"></span>en in T<span class="_ _3"></span>ab<span class="_ _1"></span>les 7 through 10. The system <span class="_ _0"></span>must write the</div><div class="t m2 xb h7 y194 ff2 fs4 fc0 sc0 ls7f ws119">CFI Exit command to return to Read mode from the CF<span class="_ _1"></span>I</div><div class="t m2 xb h7 y195 ff2 fs4 fc0 sc0 ls37 wsb5">Quer<span class="_ _0"></span>y mode<span class="_ _1"></span>.</div><div class="t m2 x2 h6 y196 ff1 fs4 fc0 sc0 ls86 ws2">T<span class="_ _3"></span>ABLE<span class="_ _5"> </span>2:<span class="_ _c"> </span>B</div><div class="t m2 x56 h6 y197 ff1 fs8 fc0 sc0 lsa6 ws2">OOT<span class="fs4 ls88"> B</span><span class="lsa7">LOCK<span class="fs4 ls88"> A</span><span class="ls89">DDRESS<span class="fs4 ls88"> R</span><span class="lsa8">ANGES</span></span></span></div><div class="t m2 x57 hb y198 ff1 fs6 fc0 sc0 lsa9 ws11a">Pro<span class="_ _1"></span>duct<span class="_ _18"> </span>Address Ra<span class="_ _1"></span>nge</div><div class="t m2 x57 hb y199 ff1 fs6 fc0 sc0 lsa5 wsa6">Bottom Boot Bloc<span class="_ _4"></span>k</div><div class="t m2 x58 h9 y19a ff2 fs6 fc0 sc0 lsaa ws2">SST39VF1601<span class="_ _1"></span>/3201/6401<span class="_ _19"> </span>000000H<span class="_ _1"></span>-007FFFH</div><div class="t m2 x57 hb y19b ff1 fs6 fc0 sc0 lsab ws11b">T<span class="_ _4"></span>op Boot Bl<span class="_ _1"></span>ock</div><div class="t m2 x58 h9 y19c ff2 fs6 fc0 sc0 lsac ws2">SST39VF1602<span class="_ _1a"> </span>0F8000H-0<span class="_ _1"></span>FFFFFH</div><div class="t m2 x58 h9 y19d ff2 fs6 fc0 sc0 lsac ws2">SST39VF3202<span class="_ _1a"> </span>1F8000H-1<span class="_ _1"></span>FFFFFH</div><div class="t m2 x58 h9 y19e ff2 fs6 fc0 sc0 lsac ws2">SST39VF6402<span class="_ _1a"> </span>3F8000H-3<span class="_ _1"></span>FFFFFH</div><div class="t m2 x59 h3 y19f ff2 fs1 fc0 sc0 ls96 ws2">T2.0<span class="_ _17"> </span>1223</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6256131947503a0a93fdda39/bg5.jpg"><div class="t m1 x1a h7 y1 ff2 fs4 fc0 sc0 ls66 wsa2">Prelimi<span class="_ _0"></span>nary Spec<span class="_ _0"></span>ificati<span class="_ _0"></span>ons</div><div class="t m1 x2 ha y67 ff1 fs7 fc0 sc0 ls3f ws4b">16 Mbit / 32 Mbit / 64 Mb<span class="_ _0"></span>it Multi-Purpose Fl<span class="_ _0"></span>ash Plus</div><div class="t m1 x2 ha y68 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1601 / SST39<span class="_ _0"></span>VF3201 / SST39<span class="_ _0"></span>VF6401</div><div class="t m1 x2 ha y69 ff1 fs7 fc0 sc0 ls40 ws4c">SST39VF1602 / SST39<span class="_ _0"></span>VF3202 / SST39<span class="_ _0"></span>VF6402</div><div class="t m1 x10 h9 y66 ff2 fs6 fc0 sc0 ls3 ws2">5</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls41 ws4d">©<span class="_ _0"></span>2003 Silicon Sto<span class="_ _0"></span>rage Technology, Inc.<span class="_ _7"> </span><span class="ls2 ws2">S71223-03<span class="_ _1"></span>-000<span class="_ _8"> </span>11/03</span></div><div class="t m1 x2 h5 y153 ff1 fs3 fc0 sc0 ls79 wsc7">Product Identifica<span class="_ _0"></span>tion</div><div class="t m1 x2 h7 y154 ff2 fs4 fc0 sc0 ls38 ws11c">The Produc<span class="_ _0"></span>t Identific<span class="_ _0"></span>ation mode <span class="_ _0"></span>identif<span class="_ _0"></span>ies the d<span class="_ _0"></span>e<span class="_ _4"></span>v<span class="_ _0"></span>ices as</div><div class="t m1 x2 h7 y155 ff2 fs4 fc0 sc0 ls77 ws11d">the SST39V<span class="_ _0"></span>F1601, S<span class="_ _0"></span>ST39VF1602, S<span class="_ _0"></span>ST39VF320<span class="_ _0"></span>1,</div><div class="t m1 x2 h7 y156 ff2 fs4 fc0 sc0 ls27 ws11e">SST39VF32<span class="_ _0"></span>02, SST39VF<span class="_ _0"></span>6401, SST<span class="_ _0"></span>39VF6402, and</div><div class="t m1 x2 h7 y1a0 ff2 fs4 fc0 sc0 ls27 ws11f">manuf<span class="_ _1"></span>acturer as<span class="_ _0"></span> SST<span class="_ _a"></span>. Thi<span class="_ _0"></span>s mode may be accessed soft-</div><div class="t m1 x2 h7 y1a1 ff2 fs4 fc0 sc0 ls27 ws120">ware operations. Users may use the Sof<span class="_ _0"></span>tware Product</div><div class="t m1 x2 h7 y1a2 ff2 fs4 fc0 sc0 lsad wsdf">Identificati<span class="_ _0"></span>on operation to identify the par<span class="_ _0"></span>t (i.e., using the</div><div class="t m1 x2 h7 y1a3 ff2 fs4 fc0 sc0 ls6b wsa7">device ID) when usi<span class="_ _0"></span>ng multiple ma<span class="_ _0"></span>nuf<span class="_ _1"></span>acturers i<span class="_ _0"></span>n the same</div><div class="t m1 x2 h7 y1a4 ff2 fs4 fc0 sc0 ls6b ws121">sock<span class="_ _1"></span>et. For details, see <span class="_ _0"></span>T<span class="_ _a"></span>a<span class="_ _0"></span>b<span class="_ _1"></span>le 6 for software op<span class="_ _0"></span>eration,</div><div class="t m1 x2 h7 y1a5 ff2 fs4 fc0 sc0 ls73 ws122">Figure 11 for the Software ID Ent<span class="_ _0"></span>r<span class="_ _0"></span>y and Read tim<span class="_ _0"></span>ing dia-</div><div class="t m1 x2 h7 y1a6 ff2 fs4 fc0 sc0 ls73 ws3b">gram and Figure 21 for the Software ID Entr<span class="_ _0"></span>y comman<span class="_ _0"></span>d</div><div class="t m1 x2 h7 y1a7 ff2 fs4 fc0 sc0 ls4d ws1b">sequence fl<span class="_ _0"></span>owchar<span class="_ _0"></span>t.</div><div class="t m1 x2 h5 y1a8 ff1 fs3 fc0 sc0 ls7c wsfa">Product Identification Mode Exit/</div><div class="t m1 x2 h5 y1a9 ff1 fs3 fc0 sc0 lsae ws123">CFI Mode Exit</div><div class="t m1 x2 h7 y1aa ff2 fs4 fc0 sc0 ls2f ws1d">In ord<span class="_ _0"></span>er to re<span class="_ _0"></span>tur<span class="_ _0"></span>n to t<span class="_ _0"></span>he stan<span class="_ _0"></span>dard Re<span class="_ _0"></span>ad mode, t<span class="_ _0"></span>he Softwar<span class="_ _0"></span>e</div><div class="t m1 x2 h7 y1ab ff2 fs4 fc0 sc0 ls32 ws124">Produc<span class="_ _0"></span>t Identifi<span class="_ _0"></span>cation m<span class="_ _0"></span>ode must be exited. Exit is<span class="_ _0"></span> accom-</div><div class="t m1 x2 h7 y1ac ff2 fs4 fc0 sc0 ls3a ws125">pli<span class="_ _1"></span>shed b<span class="_ _1"></span>y issu<span class="_ _1"></span>ing th<span class="_ _1"></span>e Soft<span class="_ _1"></span>war<span class="_ _1"></span>e ID Exi<span class="_ _1"></span>t comma<span class="_ _1"></span>nd</div><div class="t m1 x2 h7 y1ad ff2 fs4 fc0 sc0 ls59 ws126">sequ<span class="_ _0"></span>ence, which re<span class="_ _0"></span>tur<span class="_ _0"></span>ns the d<span class="_ _0"></span>e<span class="_ _1"></span>vice<span class="_ _0"></span> to the Read m<span class="_ _0"></span>ode.</div><div class="t m1 x2 h7 y1ae ff2 fs4 fc0 sc0 ls35 ws1f">This co<span class="_ _0"></span>mman<span class="_ _0"></span>d may also be<span class="_ _0"></span> used to<span class="_ _0"></span> reset<span class="_ _0"></span> the device to<span class="_ _0"></span> the</div><div class="t m1 x2 h7 y1af ff2 fs4 fc0 sc0 ls6e ws127">Read<span class="_ _1"></span> mode a<span class="_ _1"></span>fter<span class="_ _1"></span> any i<span class="_ _1"></span>nadv<span class="_ _4"></span>er<span class="_ _0"></span>tent t<span class="_ _1"></span>ransi<span class="_ _1"></span>ent<span class="_ _1"></span> condit<span class="_ _1"></span>ion th<span class="_ _1"></span>at</div><div class="t m1 x2 h7 y1b0 ff2 fs4 fc0 sc0 ls2e ws77">appare<span class="_ _0"></span>ntly c<span class="_ _0"></span>auses the<span class="_ _0"></span> device to be<span class="_ _0"></span>hav<span class="_ _1"></span>e abno<span class="_ _0"></span>r<span class="_ _0"></span>mally<span class="_ _3"></span>, <span class="_ _0"></span>e.g.,</div><div class="t m1 x2 h7 y1b1 ff2 fs4 fc0 sc0 ls32 wsfe">not read<span class="_ _0"></span> correct<span class="_ _0"></span>ly<span class="_ _3"></span>. Pl<span class="_ _0"></span>ease no<span class="_ _0"></span>te that the S<span class="_ _0"></span>oftware ID<span class="_ _0"></span> Exit/</div><div class="t m1 x2 h7 y1b2 ff2 fs4 fc0 sc0 ls2c ws128">CFI Exit c<span class="_ _0"></span>ommand<span class="_ _0"></span> is igno<span class="_ _0"></span>red dur<span class="_ _0"></span>ing an<span class="_ _0"></span> inter<span class="_ _0"></span>na<span class="_ _0"></span>l Program or</div><div class="t m1 x2 h7 y1b3 ff2 fs4 fc0 sc0 ls33 ws129">Erase op<span class="_ _0"></span>eration. S<span class="_ _0"></span>ee T<span class="_ _3"></span>abl<span class="_ _0"></span>e <span class="_ _0"></span>6<span class="_ _0"></span> for software co<span class="_ _0"></span>mmand</div><div class="t m1 x2 h7 y1b4 ff2 fs4 fc0 sc0 ls2c ws12a">codes, Figur<span class="_ _0"></span>e 13 f<span class="_ _1"></span>or timi<span class="_ _0"></span>ng wav<span class="_ _4"></span>e<span class="_ _0"></span>f<span class="_ _4"></span>o<span class="_ _0"></span>r<span class="_ _0"></span>m, and Fig<span class="_ _0"></span>ures 21 and</div><div class="t m1 x2 h7 y1b5 ff2 fs4 fc0 sc0 ls58 ws19">22 for flowchar<span class="_ _0"></span>ts.</div><div class="t m1 xb h5 y153 ff1 fs3 fc0 sc0 lsaf ws49">Security<span class="_ _1"></span> ID</div><div class="t m1 xb h7 y154 ff2 fs4 fc0 sc0 ls5f ws12b">The SS<span class="_ _0"></span>T39VF1<span class="_ _0"></span>60x/<span class="_ _0"></span>320x/640<span class="_ _0"></span>x devices o<span class="_ _0"></span>ff<span class="_ _1"></span>er a<span class="_ _0"></span> 256-bit</div><div class="t m1 xb h7 y155 ff2 fs4 fc0 sc0 ls33 wsdb">Secur<span class="_ _0"></span>ity<span class="_ _0"></span> ID space. The<span class="_ _0"></span> Secur<span class="_ _0"></span>e ID sp<span class="_ _0"></span>ace is di<span class="_ _0"></span>vided i<span class="_ _0"></span>nto two</div><div class="t m1 xb h7 y156 ff2 fs4 fc0 sc0 ls59 ws11c">128-bi<span class="_ _0"></span>t segment<span class="_ _0"></span>s - one factor<span class="_ _0"></span>y pr<span class="_ _0"></span>ogrammed seg<span class="_ _0"></span>ment an<span class="_ _0"></span>d</div><div class="t m1 xb h7 y1a0 ff2 fs4 fc0 sc0 ls5a ws12c">one user<span class="_ _0"></span> programmed seg<span class="_ _0"></span>ment. Th<span class="_ _0"></span>e first se<span class="_ _0"></span>gment is pr<span class="_ _0"></span>o-</div><div class="t m1 xb h7 y1a1 ff2 fs4 fc0 sc0 ls45 ws72">grammed an<span class="_ _0"></span>d locked at SS<span class="_ _0"></span>T with<span class="_ _0"></span> a rando<span class="_ _0"></span>m 128-<span class="_ _0"></span>bit num-</div><div class="t m1 xb h7 y1a2 ff2 fs4 fc0 sc0 ls45 ws12d">ber<span class="_ _4"></span>. T<span class="_ _0"></span>he user seg<span class="_ _0"></span>ment is le<span class="_ _0"></span>ft un-programmed<span class="_ _0"></span> f<span class="_ _1"></span>or the</div><div class="t m1 xb h7 y1a3 ff2 fs4 fc0 sc0 ls2c ws13">custom<span class="_ _0"></span>er to pr<span class="_ _0"></span>ogram as des<span class="_ _0"></span>ired.</div><div class="t m1 xb h7 y1b6 ff2 fs4 fc0 sc0 ls2f ws12e">T<span class="_ _a"></span>o pr<span class="_ _0"></span>ogram the user segm<span class="_ _0"></span>ent of the Sec<span class="_ _0"></span>urity<span class="_ _0"></span> ID<span class="_ _4"></span>, the user</div><div class="t m1 xb h7 y1b7 ff2 fs4 fc0 sc0 ls58 ws12f">must use th<span class="_ _0"></span>e Secu<span class="_ _0"></span>rity <span class="_ _0"></span>ID Word-Program comm<span class="_ _0"></span>and. T<span class="_ _3"></span>o</div><div class="t m1 xb h7 y1b8 ff2 fs4 fc0 sc0 ls5a ws130">detect en<span class="_ _0"></span>d-of-w<span class="_ _0"></span>rite for the SEC ID<span class="_ _4"></span>,<span class="_ _0"></span> read the t<span class="_ _0"></span>oggle bi<span class="_ _0"></span>ts. Do</div><div class="t m1 xb h7 y1b9 ff2 fs4 fc0 sc0 ls5c wsd3">not use <span class="_ _0"></span>Data# <span class="_ _0"></span>P<span class="_ _4"></span>oll<span class="_ _0"></span>ing. On<span class="_ _0"></span>ce this<span class="_ _0"></span> is co<span class="_ _0"></span>mplete, t<span class="_ _0"></span>he Sec I<span class="_ _0"></span>D</div><div class="t m1 xb h7 y1ba ff2 fs4 fc0 sc0 ls35 wse0">shou<span class="_ _0"></span>ld be locked using the Us<span class="_ _0"></span>er Sec ID P<span class="_ _0"></span>rogram Lock-Out.</div><div class="t m1 xb h7 y1bb ff2 fs4 fc0 sc0 ls2e wse4">This dis<span class="_ _0"></span>ables any future corr<span class="_ _0"></span>upti<span class="_ _0"></span>on of this sp<span class="_ _0"></span>ace. Note that</div><div class="t m1 xb h7 y1bc ff2 fs4 fc0 sc0 ls37 ws131">reg<span class="_ _1"></span>ardless<span class="_ _1"></span> of wh<span class="_ _1"></span>ether<span class="_ _1"></span> or no<span class="_ _1"></span>t the<span class="_ _1"></span> Sec ID<span class="_ _1"></span> is l<span class="_ _1"></span>oc<span class="_ _1"></span>ke<span class="_ _1"></span>d, nei<span class="_ _1"></span>the<span class="_ _1"></span>r</div><div class="t m1 xb h7 y1bd ff2 fs4 fc0 sc0 ls31 ws22">Sec ID s<span class="_ _0"></span>egment <span class="_ _0"></span>can b<span class="_ _0"></span>e erased.</div><div class="t m1 xb h7 y1be ff2 fs4 fc0 sc0 ls31 ws132">The Secu<span class="_ _0"></span>re ID space ca<span class="_ _0"></span>n be quer<span class="_ _0"></span>ied by e<span class="_ _4"></span>xecuting<span class="_ _0"></span> a three-</div><div class="t m1 xb h7 y1bf ff2 fs4 fc0 sc0 lsb0 ws133">b<span class="_ _1"></span>yte comm<span class="_ _1"></span>and sequ<span class="_ _1"></span>ence wit<span class="_ _1"></span>h Enter Se<span class="_ _1"></span>c ID com<span class="_ _1"></span>mand</div><div class="t m1 xb h7 y1c0 ff2 fs4 fc0 sc0 ls5a ws134">(88H) at ad<span class="_ _0"></span>dress 5555<span class="_ _0"></span>H in the last byte sequenc<span class="_ _0"></span>e. T<span class="_ _a"></span>o e<span class="_ _1"></span>xit</div><div class="t m1 xb h7 y1c1 ff2 fs4 fc0 sc0 ls6d ws135">this mo<span class="_ _1"></span>de,<span class="_ _1"></span> the Exit<span class="_ _1"></span> Sec ID comm<span class="_ _1"></span>and shou<span class="_ _1"></span>ld be e<span class="_ _4"></span>xec<span class="_ _1"></span>uted.</div><div class="t m1 xb h7 y1c2 ff2 fs4 fc0 sc0 ls2e ws12">Refer to T<span class="_ _a"></span>a<span class="_ _0"></span>ble<span class="_ _0"></span> 6 f<span class="_ _1"></span>or more detai<span class="_ _0"></span>ls.</div><div class="t m1 x2 h6 y1c3 ff1 fs4 fc0 sc0 ls86 ws2">T<span class="_ _3"></span>ABLE<span class="_ _5"> </span>3:<span class="_ _c"> </span>P</div><div class="t m1 x56 h6 y117 ff1 fs8 fc0 sc0 ls89 ws2">RODUCT<span class="fs4 ls88"> I</span><span class="lsb1">DENT<span class="_ _1"></span>IFICATI<span class="_ _1"></span>ON</span></div><div class="t m1 x5a hb y1c4 ff1 fs6 fc0 sc0 lsb2 ws2">Address<span class="_ _1b"> </span>Data</div><div class="t m1 x57 h9 y1c5 ff2 fs6 fc0 sc0 lsb3 ws136">Manuf<span class="_ _4"></span>acturer’<span class="_ _4"></span>s ID<span class="_ _1c"> </span>0000H<span class="_ _1d"> </span>BFH</div><div class="t m1 x57 h9 y1c6 ff2 fs6 fc0 sc0 lsb4 ws137">Device ID</div><div class="t m1 x58 h9 y1c7 ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF1601<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>234BH</div><div class="t m1 x58 h9 y1c8 ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF1602<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>234AH</div><div class="t m1 x58 h9 y1c9 ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF3201<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>235BH</div><div class="t m1 x58 h9 y1ca ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF3202<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>235AH</div><div class="t m1 x58 h9 y1cb ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF6401<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>236BH</div><div class="t m1 x58 h9 y1cc ff2 fs6 fc0 sc0 lsb5 ws2">SST39VF6402<span class="_ _1e"> </span>0001H<span class="_ _1f"> </span>236AH</div><div class="t m1 x59 h3 y1cd ff2 fs1 fc0 sc0 ls96 ws2">T3.2<span class="_ _17"> </span>1223</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>