msp430.rar_MSP430开发板_单片机开发_嵌入式/单片机/硬件编程下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/622b7fc815da9b288b89274e/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b7fc815da9b288b89274e/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">AT45DB041</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">1</div><div class="t m0 x3 h4 y3 ff1 fs2 fc0 sc0 ls2 ws0">Features</div><div class="t m0 x3 h3 y4 ff1 fs1 fc0 sc0 ls1 ws0">•</div><div class="t m0 x4 h5 y5 ff1 fs3 fc0 sc0 ls3 ws0">Single 2.7V - 3.6V Supply</div><div class="t m0 x3 h3 y6 ff1 fs1 fc0 sc0 ls4 ws0">•</div><div class="t m0 x4 h5 y7 ff1 fs3 fc0 sc0 ls5 ws0">Serial Interface Architecture</div><div class="t m0 x3 h3 y8 ff1 fs1 fc0 sc0 ls6 ws0">•</div><div class="t m0 x4 h5 y9 ff1 fs3 fc0 sc0 ls5 ws0">Page Program Operation</div><div class="t m0 x5 h5 ya ff1 fs3 fc0 sc0 ls3 ws0">Single Cycle Reprogram (Erase and Program)</div><div class="t m0 x5 h5 yb ff1 fs3 fc0 sc0 ls3 ws0">2048 Pages (264 Bytes/Page) Main Memory</div><div class="t m0 x3 h3 yc ff1 fs1 fc0 sc0 ls4 ws0">•</div><div class="t m0 x4 h5 yd ff1 fs3 fc0 sc0 ls3 ws0">Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of</div><div class="t m0 x4 h5 ye ff1 fs3 fc0 sc0 ls7 ws0">Non-Volatile Memory</div><div class="t m0 x3 h3 yf ff1 fs1 fc0 sc0 ls8 ws0">•</div><div class="t m0 x4 h5 y10 ff1 fs3 fc0 sc0 ls3 ws0">Internal Program and Control Timer</div><div class="t m0 x3 h3 y11 ff1 fs1 fc0 sc0 ls4 ws0">•</div><div class="t m0 x4 h5 y12 ff1 fs3 fc0 sc0 ls3 ws0">Fast Page Program Time - 7 ms Typical</div><div class="t m0 x3 h3 y13 ff1 fs1 fc0 sc0 ls4 ws0">•</div><div class="t m0 x4 h5 y14 ff1 fs3 fc0 sc0 ls7 ws0">120 ms Typical Page to Buffer Transfer Time</div><div class="t m0 x3 h3 y15 ff1 fs1 fc0 sc0 lsa ws0">•</div><div class="t m0 x4 h5 y16 ff1 fs3 fc0 sc0 ls9 ws0">Low Power Dissipation</div><div class="t m0 x5 h5 y17 ff1 fs3 fc0 sc0 ls9 ws0">4 mA Active Read Current Typical</div><div class="t m0 x5 h5 y18 ff1 fs3 fc0 sc0 ls9 ws0">8 mA CMOS Standby Current Typical</div><div class="t m0 x3 h3 y19 ff1 fs1 fc0 sc0 lsa ws0">•</div><div class="t m0 x4 h5 y1a ff1 fs3 fc0 sc0 ls5 ws0">5 MHz Max Clock Frequency</div><div class="t m0 x3 h3 y1b ff1 fs1 fc0 sc0 ls6 ws0">•</div><div class="t m0 x4 h5 y1c ff1 fs3 fc0 sc0 ls5 ws0">Hardware Data Protection Feature</div><div class="t m0 x3 h3 y1d ff1 fs1 fc0 sc0 ls6 ws0">•</div><div class="t m0 x4 h5 y1e ff1 fs3 fc0 sc0 ls3 ws0">Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3</div><div class="t m0 x3 h3 y1f ff1 fs1 fc0 sc0 ls4 ws0">•</div><div class="t m0 x4 h5 y20 ff1 fs3 fc0 sc0 ls5 ws0">CMOS and TTL Compatible Inputs and Outputs</div><div class="t m0 x3 h3 y21 ff1 fs1 fc0 sc0 ls6 ws0">•</div><div class="t m0 x4 h5 y22 ff1 fs3 fc0 sc0 ls7 ws0">Commercial and Industrial Temperature Ranges</div><div class="t m0 x3 h4 y23 ff1 fs2 fc0 sc0 lsb ws0">Description</div><div class="t m0 x3 h6 y24 ff3 fs1 fc0 sc0 lsc ws0">The AT45DB041 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-</div><div class="t m0 x3 h6 y25 ff3 fs1 fc0 sc0 lsd ws0">tem reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of</div><div class="t m0 x3 h6 y26 ff3 fs1 fc0 sc0 lse ws0">264-bytes each. In addi tion to the main memory, the AT45DB 041 als o contains two</div><div class="t m0 x3 h6 y27 ff3 fs1 fc0 sc0 ls1 ws0">data buffers of 264-bytes each. The buffers allow receiving of data while a page in the</div><div class="t m0 x3 h6 y28 ff3 fs1 fc0 sc0 lsf ws0">main memory is being reprogrammed. Unlike conventional F lash mem ories that are</div><div class="t m0 x3 h6 y29 ff3 fs1 fc0 sc0 ls1 ws0">accessed randomly with multiple address lines and a parallel interface, the DataFlash</div><div class="t m0 x3 h6 y2a ff3 fs1 fc0 sc0 ls1 ws0">uses a serial interface to sequentially access its data. The simple serial interface facil-</div><div class="t m0 x3 h6 y2b ff3 fs1 fc0 sc0 ls10 ws0">itates hardware layout, increases system reliability, minimizes switching noise, and</div><div class="t m0 x6 h7 y2c ff3 fs4 fc1 sc0 ls11 ws0">0669A-A</div><div class="t m0 x7 h2 y2d ff1 fs0 fc0 sc0 ls0 ws0">4-Megabit</div><div class="t m0 x7 h2 y2e ff1 fs0 fc0 sc0 ls12 ws0">2.7-Volt Only</div><div class="t m0 x7 h2 y2f ff1 fs0 fc0 sc0 ls13 ws0">Serial</div><div class="t m0 x7 h2 y30 ff1 fs0 fc0 sc0 ls14 ws0">DataFlash</div><div class="t m0 x8 h8 y31 ff3 fs5 fc0 sc0 ls14 ws0">™</div><div class="t m0 x7 h2 y32 ff1 fs0 fc0 sc0 ls15 ws0">AT45DB041</div><div class="t m0 x3 h4 y33 ff1 fs2 fc0 sc0 ls16 ws0">Pin Configurations</div><div class="t m0 x9 h9 y34 ff1 fs6 fc0 sc0 ls17 ws0">Pin Name Function</div><div class="t m0 x9 ha y35 ff3 fs6 fc0 sc0 ls17 ws0">CS</div><div class="t m0 xa ha y36 ff3 fs6 fc0 sc0 ls18 ws0">Chip Select</div><div class="t m0 x9 ha y37 ff3 fs6 fc0 sc0 ls19 ws0">SCK Serial Clock</div><div class="t m0 x9 ha y38 ff3 fs6 fc0 sc0 ls17 ws0">SI Serial Input</div><div class="t m0 x9 ha y39 ff3 fs6 fc0 sc0 ls1a ws0">SO Serial Output</div><div class="t m0 x9 ha y3a ff3 fs6 fc0 sc0 ls1a ws0">WP</div><div class="t m0 xa ha y3b ff3 fs6 fc0 sc0 ls1a ws0">Hardware Page Write</div><div class="t m0 xa ha y3c ff3 fs6 fc0 sc0 ls1b ws0">Protect Pin</div><div class="t m0 x9 ha y3d ff3 fs6 fc0 sc0 ls1b ws0">RESET</div><div class="t m0 xa ha y3e ff3 fs6 fc0 sc0 ls1c ws0">Chip Reset</div><div class="t m0 x9 ha y3f ff3 fs6 fc0 sc0 ls1d ws0">RDY/BUSY</div><div class="t m0 xa ha y40 ff3 fs6 fc0 sc0 ls17 ws0">Ready/Busy</div><div class="t m0 xb hb y41 ff4 fs1 fc0 sc0 lse ws0">(continued)</div><div class="t m0 xc h6 y42 ff3 fs1 fc0 sc0 ls1 ws0">PLCC</div><div class="t m1 xd hc y43 ff5 fs7 fc0 sc0 ls1e ws0">5</div><div class="t m1 xd hc y44 ff5 fs7 fc0 sc0 ls1e ws0">6</div><div class="t m1 xd hc y45 ff5 fs7 fc0 sc0 ls1e ws0">7</div><div class="t m1 xd hc y46 ff5 fs7 fc0 sc0 ls1e ws0">8</div><div class="t m1 xd hc y47 ff5 fs7 fc0 sc0 ls1e ws0">9</div><div class="t m1 xd hc y48 ff5 fs7 fc0 sc0 ls14 ws0">10</div><div class="t m1 xd hc y49 ff5 fs7 fc0 sc0 ls14 ws0">11</div><div class="t m1 xd hc y4a ff5 fs7 fc0 sc0 ls14 ws0">12</div><div class="t m1 xd hc y4b ff5 fs7 fc0 sc0 ls14 ws0">13</div><div class="t m1 xe hc y43 ff5 fs7 fc0 sc0 ls14 ws0">29</div><div class="t m1 xe hc y44 ff5 fs7 fc0 sc0 ls14 ws0">28</div><div class="t m1 xe hc y45 ff5 fs7 fc0 sc0 ls14 ws0">27</div><div class="t m1 xe hc y46 ff5 fs7 fc0 sc0 ls14 ws0">26</div><div class="t m1 xe hc y47 ff5 fs7 fc0 sc0 ls14 ws0">25</div><div class="t m1 xe hc y48 ff5 fs7 fc0 sc0 ls14 ws0">24</div><div class="t m1 xe hc y49 ff5 fs7 fc0 sc0 ls14 ws0">23</div><div class="t m1 xe hc y4a ff5 fs7 fc0 sc0 ls14 ws0">22</div><div class="t m1 xe hc y4b ff5 fs7 fc0 sc0 ls14 ws0">21</div><div class="t m1 xf hc y43 ff5 fs7 fc0 sc0 ls14 ws0">SCK</div><div class="t m1 x10 hc y44 ff5 fs7 fc0 sc0 ls14 ws0">SI</div><div class="t m1 x11 hc y45 ff5 fs7 fc0 sc0 ls14 ws0">SO</div><div class="t m1 x11 hc y46 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x11 hc y47 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x11 hc y48 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x11 hc y49 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x11 hc y4a ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x11 hc y4b ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y43 ff5 fs7 fc0 sc0 ls14 ws0">WP</div><div class="t m1 x12 hc y44 ff5 fs7 fc0 sc0 ls14 ws0">RESET</div><div class="t m1 x12 hc y45 ff5 fs7 fc0 sc0 ls14 ws0">RDY/BUSY</div><div class="t m1 x12 hc y46 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y47 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y48 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y49 ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y4a ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x12 hc y4b ff5 fs7 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x13 hd y4c ff5 fs8 fc0 sc0 ls14 ws0">4</div><div class="t m2 x14 hd y4c ff5 fs8 fc0 sc0 ls14 ws0">3</div><div class="t m2 x15 hd y4c ff5 fs8 fc0 sc0 ls14 ws0">2</div><div class="t m2 x16 hd y4c ff5 fs8 fc0 sc0 ls14 ws0">1</div><div class="t m2 x17 hd y4d ff5 fs8 fc0 sc0 ls14 ws0">32</div><div class="t m2 x18 hd y4d ff5 fs8 fc0 sc0 ls14 ws0">31</div><div class="t m2 xe hd y4d ff5 fs8 fc0 sc0 ls14 ws0">30</div><div class="t m2 x13 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">14</div><div class="t m2 x14 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">15</div><div class="t m2 x15 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">16</div><div class="t m2 x16 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">17</div><div class="t m2 x17 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">18</div><div class="t m2 x18 hd y4e ff5 fs8 fc0 sc0 ls14 ws0">19</div><div class="t m2 xe hd y4e ff5 fs8 fc0 sc0 ls14 ws0">20</div><div class="t m2 x13 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x14 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x15 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">DC</div><div class="t m2 x16 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x17 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x18 hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 xe hd y4f ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x13 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">CS</div><div class="t m2 x14 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x15 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 x16 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">GND</div><div class="t m2 x17 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">VCC</div><div class="t m2 x18 hd y50 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m2 xe hd y50 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m0 xa h6 y51 ff3 fs1 fc0 sc0 ls1f ws0">TSOP Top View</div><div class="t m0 x19 h6 y52 ff3 fs1 fc0 sc0 ls20 ws0">Ty pe 1</div><div class="t m3 x1a he y53 ff5 fs9 fc0 sc0 ls21 ws0">1</div><div class="t m3 x1a he y54 ff5 fs9 fc0 sc0 ls21 ws0">2</div><div class="t m3 x1a he y55 ff5 fs9 fc0 sc0 ls21 ws0">3</div><div class="t m3 x1a he y56 ff5 fs9 fc0 sc0 ls21 ws0">4</div><div class="t m3 x1a he y57 ff5 fs9 fc0 sc0 ls21 ws0">5</div><div class="t m3 x1a he y58 ff5 fs9 fc0 sc0 ls21 ws0">6</div><div class="t m3 x1a he y59 ff5 fs9 fc0 sc0 ls21 ws0">7</div><div class="t m3 x1a he y5a ff5 fs9 fc0 sc0 ls21 ws0">8</div><div class="t m3 x1a he y5b ff5 fs9 fc0 sc0 ls21 ws0">9</div><div class="t m3 x1a he y5c ff5 fs9 fc0 sc0 ls14 ws0">10</div><div class="t m3 x1a he y5d ff5 fs9 fc0 sc0 ls14 ws0">11</div><div class="t m3 x1a he y5e ff5 fs9 fc0 sc0 ls14 ws0">12</div><div class="t m3 x1a he y5f ff5 fs9 fc0 sc0 ls14 ws0">13</div><div class="t m3 x1a he y60 ff5 fs9 fc0 sc0 ls14 ws0">14</div><div class="t m3 x1b he y61 ff5 fs9 fc0 sc0 ls14 ws0">28</div><div class="t m3 x1b he y62 ff5 fs9 fc0 sc0 ls14 ws0">27</div><div class="t m3 x1b he y63 ff5 fs9 fc0 sc0 ls14 ws0">26</div><div class="t m3 x1b he y64 ff5 fs9 fc0 sc0 ls14 ws0">25</div><div class="t m3 x1b he y65 ff5 fs9 fc0 sc0 ls14 ws0">24</div><div class="t m3 x1b he y66 ff5 fs9 fc0 sc0 ls14 ws0">23</div><div class="t m3 x1b he y67 ff5 fs9 fc0 sc0 ls14 ws0">22</div><div class="t m3 x1b he y68 ff5 fs9 fc0 sc0 ls14 ws0">21</div><div class="t m3 x1b he y69 ff5 fs9 fc0 sc0 ls14 ws0">20</div><div class="t m3 x1b he y6a ff5 fs9 fc0 sc0 ls14 ws0">19</div><div class="t m3 x1b he y6b ff5 fs9 fc0 sc0 ls14 ws0">18</div><div class="t m3 x1b he y6c ff5 fs9 fc0 sc0 ls14 ws0">17</div><div class="t m3 x1b he y6d ff5 fs9 fc0 sc0 ls14 ws0">16</div><div class="t m3 x1b he y6e ff5 fs9 fc0 sc0 ls14 ws0">15</div><div class="t m3 x1c he y53 ff5 fs9 fc0 sc0 ls14 ws0">RDY/BUSY</div><div class="t m3 x1d he y54 ff5 fs9 fc0 sc0 ls14 ws0">RESET</div><div class="t m3 x1e he y55 ff5 fs9 fc0 sc0 ls14 ws0">WP</div><div class="t m3 x1f he y56 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x1f he y57 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x20 he y58 ff5 fs9 fc0 sc0 ls14 ws0">VCC</div><div class="t m3 x20 he y59 ff5 fs9 fc0 sc0 ls14 ws0">GND</div><div class="t m3 x1f he y5a ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x1f he y5b ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x1f he y5c ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x1f he y5d ff5 fs9 fc0 sc0 ls14 ws0">CS</div><div class="t m3 x20 he y5e ff5 fs9 fc0 sc0 ls14 ws0">SCK</div><div class="t m3 x21 he y5f ff5 fs9 fc0 sc0 ls14 ws0">SI</div><div class="t m3 x1f he y60 ff5 fs9 fc0 sc0 ls14 ws0">SO</div><div class="t m3 x22 he y61 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y62 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y63 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y64 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y65 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y66 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y67 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y68 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y69 ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y6a ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y6b ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y6c ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y6d ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m3 x22 he y6e ff5 fs9 fc0 sc0 ls14 ws0">NC</div><div class="t m0 x14 h6 y51 ff3 fs1 fc0 sc0 ls22 ws0">SOIC</div><div class="t m1 xc hd y6f ff5 fs8 fc0 sc0 ls23 ws0">1</div><div class="t m1 xc hd y70 ff5 fs8 fc0 sc0 ls23 ws0">2</div><div class="t m1 xc hd y71 ff5 fs8 fc0 sc0 ls23 ws0">3</div><div class="t m1 xc hd y72 ff5 fs8 fc0 sc0 ls23 ws0">4</div><div class="t m1 xc hd y73 ff5 fs8 fc0 sc0 ls23 ws0">5</div><div class="t m1 xc hd y74 ff5 fs8 fc0 sc0 ls23 ws0">6</div><div class="t m1 xc hd y75 ff5 fs8 fc0 sc0 ls23 ws0">7</div><div class="t m1 xc hd y76 ff5 fs8 fc0 sc0 ls23 ws0">8</div><div class="t m1 xc hd y77 ff5 fs8 fc0 sc0 ls23 ws0">9</div><div class="t m1 xc hd y78 ff5 fs8 fc0 sc0 ls14 ws0">10</div><div class="t m1 xc hd y79 ff5 fs8 fc0 sc0 ls14 ws0">11</div><div class="t m1 xc hd y7a ff5 fs8 fc0 sc0 ls14 ws0">12</div><div class="t m1 xc hd y7b ff5 fs8 fc0 sc0 ls14 ws0">13</div><div class="t m1 xc hd y7c ff5 fs8 fc0 sc0 ls14 ws0">14</div><div class="t m1 x17 hd y6f ff5 fs8 fc0 sc0 ls14 ws0">28</div><div class="t m1 x17 hd y70 ff5 fs8 fc0 sc0 ls14 ws0">27</div><div class="t m1 x17 hd y71 ff5 fs8 fc0 sc0 ls14 ws0">26</div><div class="t m1 x17 hd y72 ff5 fs8 fc0 sc0 ls14 ws0">25</div><div class="t m1 x17 hd y73 ff5 fs8 fc0 sc0 ls14 ws0">24</div><div class="t m1 x17 hd y74 ff5 fs8 fc0 sc0 ls14 ws0">23</div><div class="t m1 x17 hd y75 ff5 fs8 fc0 sc0 ls14 ws0">22</div><div class="t m1 x17 hd y76 ff5 fs8 fc0 sc0 ls14 ws0">21</div><div class="t m1 x17 hd y77 ff5 fs8 fc0 sc0 ls14 ws0">20</div><div class="t m1 x17 hd y78 ff5 fs8 fc0 sc0 ls14 ws0">19</div><div class="t m1 x17 hd y79 ff5 fs8 fc0 sc0 ls14 ws0">18</div><div class="t m1 x17 hd y7a ff5 fs8 fc0 sc0 ls14 ws0">17</div><div class="t m1 x17 hd y7b ff5 fs8 fc0 sc0 ls14 ws0">16</div><div class="t m1 x17 hd y7c ff5 fs8 fc0 sc0 ls14 ws0">15</div><div class="t m1 x23 hd y6f ff5 fs8 fc0 sc0 ls14 ws0">VSS</div><div class="t m1 x24 hd y70 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y71 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y72 ff5 fs8 fc0 sc0 ls14 ws0">CS</div><div class="t m1 x23 hd y73 ff5 fs8 fc0 sc0 ls14 ws0">SCK</div><div class="t m1 x25 hd y74 ff5 fs8 fc0 sc0 ls14 ws0">SI</div><div class="t m1 x24 hd y75 ff5 fs8 fc0 sc0 ls14 ws0">SO</div><div class="t m1 x24 hd y76 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y77 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y78 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y79 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y7a ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y7b ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x24 hd y7c ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y6f ff5 fs8 fc0 sc0 ls14 ws0">VCC</div><div class="t m1 x26 hd y70 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y71 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y72 ff5 fs8 fc0 sc0 ls14 ws0">WP</div><div class="t m1 x26 hd y73 ff5 fs8 fc0 sc0 ls14 ws0">RESET</div><div class="t m1 x26 hd y74 ff5 fs8 fc0 sc0 ls14 ws0">RDY/BUSY</div><div class="t m1 x26 hd y75 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y76 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y77 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y78 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y79 ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y7a ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y7b ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m1 x26 hd y7c ff5 fs8 fc0 sc0 ls14 ws0">NC</div><div class="t m0 x27 hf y7d ff3 fs3 fc0 sc0 ls7 ws0">Note: PLCC package pin 16</div><div class="t m0 x27 hf y7e ff3 fs3 fc0 sc0 ls24 ws0">is DON’T CONNECT.</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b7fc815da9b288b89274e/bg2.jpg"><div class="t m0 x28 h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">AT45DB041</div><div class="t m0 x3 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">2</div><div class="t m0 x3 h4 y80 ff1 fs2 fc0 sc0 ls2 ws0">Device Operation</div><div class="t m0 x3 h6 y81 ff3 fs1 fc0 sc0 lsf ws0">The device operation is controlled by instructions from the</div><div class="t m0 x3 h6 y82 ff3 fs1 fc0 sc0 ls22 ws0">host processor. The list of instructions and their associated</div><div class="t m0 x3 h6 y83 ff3 fs1 fc0 sc0 lsf ws0">opcodes are c onta in ed in Tables 1 and 2 . A vali d i ns tr uc -</div><div class="t m0 x3 h6 y84 ff3 fs1 fc0 sc0 ls1 ws0">tion starts with the falling edge of CS</div><div class="t m0 x29 h6 y85 ff3 fs1 fc0 sc0 ls1 ws0">followed by the appro-</div><div class="t m0 x3 h6 y86 ff3 fs1 fc0 sc0 ls1 ws0">priate 8-bit opcode and the desired buffer or main memory</div><div class="t m0 x3 h6 y87 ff3 fs1 fc0 sc0 ls1 ws0">address location. While the CS</div><div class="t m0 x2a h6 y88 ff3 fs1 fc0 sc0 ls1 ws0">pin is low, toggling the SCK</div><div class="t m0 x3 h6 y89 ff3 fs1 fc0 sc0 ls25 ws0">pin co ntrol s the load ing o f the o pcod e and the desir ed</div><div class="t m0 x3 h6 y8a ff3 fs1 fc0 sc0 ls25 ws0">buffer or ma in memory addres s locatio n throug h the SI</div><div class="t m0 x3 h6 y8b ff3 fs1 fc0 sc0 lsf ws0">(serial input) pin. All instructions, addresses, and data are</div><div class="t m0 x3 h6 y8c ff3 fs1 fc0 sc0 ls1 ws0">transferred with the most significant bit (MSB) first.</div><div class="t m0 x3 h10 y8d ff1 fsa fc0 sc0 ls26 ws0">Read</div><div class="t m0 x3 h6 y8e ff3 fs1 fc0 sc0 ls27 ws0">By specifying the appropriate opcode, data can be read</div><div class="t m0 x3 h6 y8f ff3 fs1 fc0 sc0 lsd ws0">from the main memory or from either one of the two data</div><div class="t m0 x3 h6 y90 ff3 fs1 fc0 sc0 ls1 ws0">buffers.</div><div class="t m0 x3 h3 y91 ff1 fs1 fc0 sc0 ls28 ws0">MAIN MEMORY PAGE READ:</div><div class="t m0 x2b h6 y92 ff3 fs1 fc0 sc0 ls1 ws0">A main memory read allows</div><div class="t m0 x3 h6 y93 ff3 fs1 fc0 sc0 ls25 ws0">the user t o read data directly from any one of the 2048</div><div class="t m0 x3 h6 y94 ff3 fs1 fc0 sc0 ls1 ws0">pages in the main memory, bypassing both of the data buff-</div><div class="t m0 x3 h6 y95 ff3 fs1 fc0 sc0 lse ws0">ers and leaving the contents of the buffers unchanged. To</div><div class="t m0 x3 h6 y96 ff3 fs1 fc0 sc0 lsf ws0">start a page read, the 8-bit opcode, 52H, is followed by 24</div><div class="t m0 x2c h6 y97 ff3 fs1 fc0 sc0 ls1 ws0">address bits and 32 don’t care bits. In the AT45DB041, the</div><div class="t m0 x2c h6 y98 ff3 fs1 fc0 sc0 ls29 ws0">first four address bits are reserved for larger density</div><div class="t m0 x2c h6 y99 ff3 fs1 fc0 sc0 lsd ws0">devices (see Notes on page 7), the next 11 address bits</div><div class="t m0 x2c h6 y9a ff3 fs1 fc0 sc0 ls2a ws0">(PA10-PA0) specify the page address, and the next nine</div><div class="t m0 x2c h6 y9b ff3 fs1 fc0 sc0 ls2a ws0">address bits (BA8-BA0) specify the starting byte address</div><div class="t m0 x2c h6 y9c ff3 fs1 fc0 sc0 lsf ws0">within the page. The 32 don’t care b its which follow the 24</div><div class="t m0 x2c h6 y9d ff3 fs1 fc0 sc0 ls2a ws0">address bits are sent to initialize the read operation. F ol-</div><div class="t m0 x2c h6 y9e ff3 fs1 fc0 sc0 ls25 ws0">lowing the 32 don’t care bits, additional pulses on SCK</div><div class="t m0 x2c h6 y9f ff3 fs1 fc0 sc0 lse ws0">result in serial data b eing output on the SO ( serial output)</div><div class="t m0 x2c h6 ya0 ff3 fs1 fc0 sc0 ls6 ws0">pin. The CS</div><div class="t m0 x26 h6 ya1 ff3 fs1 fc0 sc0 lse ws0">pin must remain low during the loading of the</div><div class="t m0 x2c h6 ya2 ff3 fs1 fc0 sc0 ls2a ws0">opcode, the address bits, and the reading of data. When</div><div class="t m0 x2c h6 ya3 ff3 fs1 fc0 sc0 ls1 ws0">the end of a page in main memory is reached during a main</div><div class="t m0 x2c h6 ya4 ff3 fs1 fc0 sc0 lse ws0">memory page read, the device will continue reading at the</div><div class="t m0 x2c h6 ya5 ff3 fs1 fc0 sc0 ls1 ws0">beginning of the same page. A low to high transition on the</div><div class="t m0 x2c h6 ya6 ff3 fs1 fc0 sc0 ls2b ws0">CS</div><div class="t m0 x2d h6 ya7 ff3 fs1 fc0 sc0 ls2a ws0">pin will ter minate the read operation and tri-state the</div><div class="t m0 x2c h6 ya8 ff3 fs1 fc0 sc0 ls22 ws0">SO pin.</div><div class="t m0 x2c h3 ya9 ff1 fs1 fc0 sc0 ls2c ws0">BUFFER READ:</div><div class="t m0 x2e h6 yaa ff3 fs1 fc0 sc0 lse ws0">Data c an be read from e ith er on e of the</div><div class="t m0 x2c h6 yab ff3 fs1 fc0 sc0 ls1 ws0">two buffers, using different opcodes to specify which buffer</div><div class="t m0 x2c h6 yac ff3 fs1 fc0 sc0 lse ws0">to read from. A n opc ode of 54H is us ed to read data from</div><div class="t m0 x2c h6 yad ff3 fs1 fc0 sc0 lse ws0">buffer 1, and an opcode o f 5 6H is used to read data from</div><div class="t m0 x3 h4 yae ff1 fs2 fc0 sc0 ls16 ws0">Block Diagram</div><div class="t m4 x2f h11 yaf ff5 fsb fc0 sc0 ls14 ws0">FLASH MEMORY ARRAY</div><div class="t m4 x30 h11 yb0 ff5 fsb fc0 sc0 ls14 ws0">PAGE (264 BYTES)</div><div class="t m4 x31 h11 yb1 ff5 fsb fc0 sc0 ls14 ws0">BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)</div><div class="t m4 xd h11 yb2 ff5 fsb fc0 sc0 ls14 ws0">I/O INTERFACE</div><div class="t m4 x32 h11 yb3 ff5 fsb fc0 sc0 ls14 ws0">SCK</div><div class="t m4 x33 h11 yb4 ff5 fsb fc0 sc0 ls14 ws0">CS</div><div class="t m4 xa h11 yb5 ff5 fsb fc0 sc0 ls14 ws0">RESET</div><div class="t m4 x34 h11 yb6 ff5 fsb fc0 sc0 ls14 ws0">V</div><div class="t m5 x35 h12 yb7 ff5 fsc fc0 sc0 ls14 ws0">CC</div><div class="t m4 x36 h11 yb8 ff5 fsb fc0 sc0 ls14 ws0">GND</div><div class="t m4 x37 h11 yb9 ff5 fsb fc0 sc0 ls14 ws0">RDY/BUSY</div><div class="t m4 x38 h11 yba ff5 fsb fc0 sc0 ls14 ws0">WP</div><div class="t m4 x39 h11 ybb ff5 fsb fc0 sc0 ls14 ws0">SOSI</div><div class="t m0 x3 h6 ybc ff3 fs1 fc0 sc0 lsf ws0">reduces p ack age size and a ctiv e pin coun t. The device is</div><div class="t m0 x3 h6 ybd ff3 fs1 fc0 sc0 lsf ws0">optimized for use in many commercial and industrial appli-</div><div class="t m0 x3 h6 ybe ff3 fs1 fc0 sc0 ls22 ws0">cations where high density, low pin count, low voltage, and</div><div class="t m0 x3 h6 ybf ff3 fs1 fc0 sc0 ls29 ws0">low power are essential. Typical applications for the</div><div class="t m0 x3 h6 yc0 ff3 fs1 fc0 sc0 lsd ws0">DataFl ash ar e di git al voic e stor age, ima ge st orage, a nd</div><div class="t m0 x3 h6 yc1 ff3 fs1 fc0 sc0 lsf ws0">data storage. The device operates at clock frequencies up</div><div class="t m0 x3 h6 yc2 ff3 fs1 fc0 sc0 lsf ws0">to 5 Mhz with a typical active r ead current c onsumption of</div><div class="t m0 x3 h6 yc3 ff3 fs1 fc0 sc0 ls2d ws0">4mA.</div><div class="t m0 x3 h6 yc4 ff3 fs1 fc0 sc0 ls29 ws0">To allow for s imple in-sy stem reprogrammability, the</div><div class="t m0 x3 h6 yc5 ff3 fs1 fc0 sc0 ls2a ws0">AT45DB041 does not require high input voltages for pro-</div><div class="t m0 x2c h6 yc6 ff3 fs1 fc0 sc0 lse ws0">gramming . The device operates from a single power sup-</div><div class="t m0 x2c h6 yc7 ff3 fs1 fc0 sc0 ls25 ws0">ply, 2.7V to 3.6V, for both the program and read opera-</div><div class="t m0 x2c h6 yc8 ff3 fs1 fc0 sc0 lse ws0">tions. T he A T45DB 041 is enabl ed through the chip selec t</div><div class="t m0 x2c h6 yc9 ff3 fs1 fc0 sc0 ls28 ws0">pin (CS</div><div class="t m0 x3a h6 yca ff3 fs1 fc0 sc0 ls1 ws0">) and accessed via a three-wire interface consisting</div><div class="t m0 x2c h6 ycb ff3 fs1 fc0 sc0 lsf ws0">of the Seria l Inp ut ( SI), Ser ia l O utput (SO), an d the Serial</div><div class="t m0 x2c h6 ycc ff3 fs1 fc0 sc0 ls22 ws0">Clock (SCK).</div><div class="t m0 x2c h6 ycd ff3 fs1 fc0 sc0 ls2e ws0">All programming cycles are self-timed, and no separate</div><div class="t m0 x2c h6 yce ff3 fs1 fc0 sc0 ls1 ws0">erase cycle is required before programming.</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b7fc815da9b288b89274e/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">AT45DB041</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">3</div><div class="t m0 x3 h6 ycf ff3 fs1 fc0 sc0 ls25 ws0">buffer 2 . To perform a buffer r ead, the eig ht bits of the</div><div class="t m0 x3 h6 yd0 ff3 fs1 fc0 sc0 ls2f ws0">opcode must be followed by 15 don’t care bits, nine</div><div class="t m0 x3 h6 yd1 ff3 fs1 fc0 sc0 ls1 ws0">address bits, and eight don't care bits. Since the buffer size</div><div class="t m0 x3 h6 yd2 ff3 fs1 fc0 sc0 lsf ws0">is 2 64-bytes , nine address bits (BFA8-BFA 0) are required</div><div class="t m0 x3 h6 yd3 ff3 fs1 fc0 sc0 lse ws0">to s pec if y t he fir st byte of data to be rea d from the buff er.</div><div class="t m0 x3 h6 yd4 ff3 fs1 fc0 sc0 ls30 ws0">The CS</div><div class="t m0 x3b h6 yd5 ff3 fs1 fc0 sc0 ls31 ws0">pin must remain low during the loading of the</div><div class="t m0 x3 h6 yd6 ff3 fs1 fc0 sc0 ls1 ws0">opcode, the address bits, the don’t care bits, and the read-</div><div class="t m0 x3 h6 yd7 ff3 fs1 fc0 sc0 ls1 ws0">ing of data. When the end of a buffer is reached, the device</div><div class="t m0 x3 h6 yd8 ff3 fs1 fc0 sc0 ls1 ws0">will continue reading back at the beginning of the buffer. A</div><div class="t m0 x3 h6 yd9 ff3 fs1 fc0 sc0 lsc ws0">low to high transition on the CS</div><div class="t m0 x3c h6 yda ff3 fs1 fc0 sc0 lsc ws0">pin will terminate the read</div><div class="t m0 x3 h6 ydb ff3 fs1 fc0 sc0 ls1 ws0">operation and tri-state the SO pin.</div><div class="t m0 x3 h3 ydc ff1 fs1 fc0 sc0 lse ws0">MAIN MEMORY PAGE TO BUFFER TRANSFER:</div><div class="t m0 x3d h6 ydd ff3 fs1 fc0 sc0 ls32 ws0">Apage</div><div class="t m0 x3 h6 yde ff3 fs1 fc0 sc0 lsf ws0">of data can be t ransferred f rom the main memory to either</div><div class="t m0 x3 h6 ydf ff3 fs1 fc0 sc0 lse ws0">buffer 1 or buffer 2. An 8-bit opc ode, 5 3H for buffer 1 and</div><div class="t m0 x3 h6 ye0 ff3 fs1 fc0 sc0 ls2a ws0">55H for buffer 2, is followed by the four reserved bits, 11</div><div class="t m0 x3 h6 ye1 ff3 fs1 fc0 sc0 ls2a ws0">address bits (PA10-PA0) which specify the page in main</div><div class="t m0 x3 h6 ye2 ff3 fs1 fc0 sc0 lse ws0">memory that is to be transferred, and nine don’t care bits.</div><div class="t m0 x3 h6 ye3 ff3 fs1 fc0 sc0 ls6 ws0">The CS</div><div class="t m0 x3e h6 ye4 ff3 fs1 fc0 sc0 ls1 ws0">pin must be low while toggling the SCK pin to load</div><div class="t m0 x3 h6 ye5 ff3 fs1 fc0 sc0 lsf ws0">the opcode, the addr ess bits, and the don’t care bits from</div><div class="t m0 x3 h6 ye6 ff3 fs1 fc0 sc0 lse ws0">the SI pin. The transfer of the page of data from the main</div><div class="t m0 x3 h6 ye7 ff3 fs1 fc0 sc0 ls1 ws0">memory to the buffer will begin when the CS</div><div class="t m0 x3f h6 ye8 ff3 fs1 fc0 sc0 lsf ws0">pin transitions</div><div class="t m0 x3 h6 ye9 ff3 fs1 fc0 sc0 lse ws0">from a low to a high state. During the transfer of a page of</div><div class="t m0 x3 h6 yea ff3 fs1 fc0 sc0 ls33 ws0">data (t</div><div class="t m0 x21 h7 yeb ff3 fs4 fc0 sc0 ls34 ws0">XFR</div><div class="t m0 x40 h6 yec ff3 fs1 fc0 sc0 lsd ws0">), th e status reg iste r c an be read to det ermine</div><div class="t m0 x3 h6 yed ff3 fs1 fc0 sc0 ls1 ws0">whether the transfer has been completed or not.</div><div class="t m0 x3 h3 yee ff1 fs1 fc0 sc0 ls35 ws0">MAIN MEM ORY PAGE TO BUFFER COM PARE:</div><div class="t m0 x3d h6 yef ff3 fs1 fc0 sc0 lsd ws0">A page</div><div class="t m0 x3 h6 yf0 ff3 fs1 fc0 sc0 lsd ws0">of da ta in main me mory can be com pare d t o t he data in</div><div class="t m0 x3 h6 yf1 ff3 fs1 fc0 sc0 lse ws0">buffer 1 or buffer 2. An 8-bit opc ode, 6 0H for buffer 1 and</div><div class="t m0 x3 h6 yf2 ff3 fs1 fc0 sc0 ls22 ws0">61H for buffer 2, is followed by 24 address bits consisting of</div><div class="t m0 x3 h6 yf3 ff3 fs1 fc0 sc0 lse ws0">the four res erv ed bits, 11 address bits (P A 10- P A0) whi ch</div><div class="t m0 x3 h6 yf4 ff3 fs1 fc0 sc0 ls27 ws0">specify the page in the main memory that is to be com-</div><div class="t m0 x3 h6 yf5 ff3 fs1 fc0 sc0 ls1 ws0">pared to the buffer, and nine don't care bits. The loading of</div><div class="t m0 x3 h6 yf6 ff3 fs1 fc0 sc0 lsf ws0">the opcode and the address bits is the same as described</div><div class="t m0 x3 h6 yf7 ff3 fs1 fc0 sc0 ls22 ws0">previously. The CS</div><div class="t m0 x41 h6 yf8 ff3 fs1 fc0 sc0 ls22 ws0">pin must be low while toggling the SCK</div><div class="t m0 x3 h6 yf9 ff3 fs1 fc0 sc0 ls22 ws0">pin to load the opcode, the address bits, and the don't care</div><div class="t m0 x3 h6 yfa ff3 fs1 fc0 sc0 ls22 ws0">bits from the SI pin. On the low to high transition of the CS</div><div class="t m0 x3 h6 yfb ff3 fs1 fc0 sc0 lsf ws0">pin, th e 264 b yt es in the selec ted mai n memor y page will</div><div class="t m0 x3 h6 yfc ff3 fs1 fc0 sc0 ls1 ws0">be compared with the 264 bytes in buffer 1 or buffer 2. Dur-</div><div class="t m0 x3 h6 yfd ff3 fs1 fc0 sc0 lsc ws0">ing this time (t</div><div class="t m0 x42 h7 yfe ff3 fs4 fc0 sc0 ls36 ws0">XFR</div><div class="t m0 x43 h6 yff ff3 fs1 fc0 sc0 lse ws0">), the status register will indicate that the</div><div class="t m0 x3 h6 y100 ff3 fs1 fc0 sc0 ls22 ws0">part is busy. On completion of the compare operation, bit 6</div><div class="t m0 x3 h6 y101 ff3 fs1 fc0 sc0 ls28 ws0">of the status register is updated with the result of the com-</div><div class="t m0 x3 h6 y102 ff3 fs1 fc0 sc0 ls1 ws0">pare.</div><div class="t m0 x3 h10 y103 ff1 fsa fc0 sc0 ls37 ws0">Program</div><div class="t m0 x3 h3 y104 ff1 fs1 fc0 sc0 ls38 ws0">BUFFER WRITE:</div><div class="t m0 x44 h6 y105 ff3 fs1 fc0 sc0 ls39 ws0">DatacanbeshiftedinfromtheSIpin</div><div class="t m0 x3 h6 y106 ff3 fs1 fc0 sc0 ls25 ws0">into e ither bu ffer 1 or buffe r 2 . To lo ad data i nto eit her</div><div class="t m0 x3 h6 y107 ff3 fs1 fc0 sc0 ls1 ws0">buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,</div><div class="t m0 x3 h6 y108 ff3 fs1 fc0 sc0 ls31 ws0">is followed by 15 don't care bits and nine address bits</div><div class="t m0 x3 h6 y109 ff3 fs1 fc0 sc0 ls1 ws0">(BFA8-BFA0). The nine address bits specify the first byte in</div><div class="t m0 x3 h6 y10a ff3 fs1 fc0 sc0 ls3a ws0">thebuffertobewritten.Thedataisenteredfollowingthe</div><div class="t m0 x3 h6 y10b ff3 fs1 fc0 sc0 lsd ws0">address bits. If the end of the data buffer is reached, the</div><div class="t m0 x3 h6 y10c ff3 fs1 fc0 sc0 ls1 ws0">device will wrap around back to the beginning of the buffer.</div><div class="t m0 x3 h6 y10d ff3 fs1 fc0 sc0 ls1 ws0">Data will continue to be loaded into the buffer until a low to</div><div class="t m0 x3 h6 y10e ff3 fs1 fc0 sc0 ls1 ws0">high transition is detected on the CS</div><div class="t m0 x29 h6 y10f ff3 fs1 fc0 sc0 ls1 ws0">pin.</div><div class="t m0 x2c h3 y110 ff1 fs1 fc0 sc0 ls3b ws0">BUFFER TO MAIN MEMORY PAGE PROGRAM WITH</div><div class="t m0 x2c h3 y111 ff1 fs1 fc0 sc0 ls28 ws0">BUILT-IN ERASE:</div><div class="t m0 x45 h6 y112 ff3 fs1 fc0 sc0 ls28 ws0">Data written into either buffer 1 or buffer</div><div class="t m0 x2c h6 y113 ff3 fs1 fc0 sc0 ls3c ws0">2 can be programmed into the main memory . An 8 -bit</div><div class="t m0 x2c h6 y114 ff3 fs1 fc0 sc0 ls1 ws0">opcode, 83H for buffer 1 or 86H for buffer 2, is followed by</div><div class="t m0 x2c h6 y115 ff3 fs1 fc0 sc0 ls27 ws0">the four reserved bits, 11 address bits (PA10-PA0) that</div><div class="t m0 x2c h6 y116 ff3 fs1 fc0 sc0 ls27 ws0">specify the page in the main memory to be written, and</div><div class="t m0 x2c h6 y117 ff3 fs1 fc0 sc0 ls1 ws0">nine additional don't care bits. When a low to high transition</div><div class="t m0 x2c h6 y118 ff3 fs1 fc0 sc0 lse ws0">occurs on the CS</div><div class="t m0 x46 h6 y119 ff3 fs1 fc0 sc0 lsf ws0">pin, the part wi ll first erase t he selected</div><div class="t m0 x2c h6 y11a ff3 fs1 fc0 sc0 lse ws0">page in main memory to all 1s and then program the data</div><div class="t m0 x2c h6 y11b ff3 fs1 fc0 sc0 ls27 ws0">stored in th e buffer into the s pecifie d page i n the main</div><div class="t m0 x2c h6 y11c ff3 fs1 fc0 sc0 ls1 ws0">memory. Both the erase and the programming of the page</div><div class="t m0 x2c h6 y11d ff3 fs1 fc0 sc0 ls3d ws0">are internally self timed and should take place in a maxi-</div><div class="t m0 x2c h6 y11e ff3 fs1 fc0 sc0 lsd ws0">mum time of t</div><div class="t m0 x12 h7 y11f ff3 fs4 fc0 sc0 ls34 ws0">EP</div><div class="t m0 x47 h6 y120 ff3 fs1 fc0 sc0 ls2a ws0">. During this ti me, the status register will</div><div class="t m0 x2c h6 y121 ff3 fs1 fc0 sc0 ls28 ws0">indicate that the part is busy.</div><div class="t m0 x2c h3 y122 ff1 fs1 fc0 sc0 ls2e ws0">BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-</div><div class="t m0 x2c h3 y123 ff1 fs1 fc0 sc0 ls33 ws0">OUT BUILT-IN ERASE:</div><div class="t m0 x48 h6 y124 ff3 fs1 fc0 sc0 ls2a ws0">A previous ly erased page within</div><div class="t m0 x2c h6 y125 ff3 fs1 fc0 sc0 ls25 ws0">main memory can be prog rammed with the c ontents of</div><div class="t m0 x2c h6 y126 ff3 fs1 fc0 sc0 ls1 ws0">either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1</div><div class="t m0 x2c h6 y127 ff3 fs1 fc0 sc0 ls1 ws0">or 89H for buffer 2, is followed by the four reserved bits, 11</div><div class="t m0 x2c h6 y128 ff3 fs1 fc0 sc0 lsf ws0">address bits (PA10-PA0) that specify the page in the main</div><div class="t m0 x2c h6 y129 ff3 fs1 fc0 sc0 lse ws0">memor y to be writt en , and nine addi tional d on ’ t care bits.</div><div class="t m0 x2c h6 y12a ff3 fs1 fc0 sc0 ls22 ws0">When a low to high transition occurs on the CS</div><div class="t m0 x49 h6 y12b ff3 fs1 fc0 sc0 lse ws0">pin, the part</div><div class="t m0 x2c h6 y12c ff3 fs1 fc0 sc0 lsf ws0">will program the data stored in the buffer into the specified</div><div class="t m0 x2c h6 y12d ff3 fs1 fc0 sc0 lsf ws0">page in the main memory. It is necessary that the page in</div><div class="t m0 x2c h6 y12e ff3 fs1 fc0 sc0 ls2a ws0">main memory that is bein g pro grammed has been previ-</div><div class="t m0 x2c h6 y12f ff3 fs1 fc0 sc0 ls2a ws0">ously programmed to all 1s (erased state). The program-</div><div class="t m0 x2c h6 y130 ff3 fs1 fc0 sc0 ls2a ws0">ming of the page is internally se lf ti med an d sh ould take</div><div class="t m0 x2c h6 y131 ff3 fs1 fc0 sc0 lsf ws0">place in a maximum time of t</div><div class="t m0 x4a h7 y132 ff3 fs4 fc0 sc0 ls3e ws0">P</div><div class="t m0 x4b h6 y133 ff3 fs1 fc0 sc0 ls28 ws0">. During this time, the status</div><div class="t m0 x2c h6 y134 ff3 fs1 fc0 sc0 ls22 ws0">register will indicate that the part is busy.</div><div class="t m0 x2c h3 y135 ff1 fs1 fc0 sc0 ls27 ws0">MAIN ME MORY PAGE PROGRAM:</div><div class="t m0 x4c h6 y136 ff3 fs1 fc0 sc0 ls27 ws0">This operation i s a</div><div class="t m0 x2c h6 y137 ff3 fs1 fc0 sc0 ls1 ws0">combination of the Buffer Write and Buffer to Main Memory</div><div class="t m0 x2c h6 y138 ff3 fs1 fc0 sc0 lsf ws0">Page Prog ram with B uilt -In Erase op era tion s. Data is f irst</div><div class="t m0 x2c h6 y139 ff3 fs1 fc0 sc0 ls1 ws0">shifted into buffer 1 or buffer 2 from the SI pin and then pro-</div><div class="t m0 x2c h6 y13a ff3 fs1 fc0 sc0 lsf ws0">grammed into a specified page in the main memory. An 8-</div><div class="t m0 x2c h6 y13b ff3 fs1 fc0 sc0 ls1 ws0">bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed</div><div class="t m0 x2c h6 y13c ff3 fs1 fc0 sc0 ls1 ws0">by the four reserved bits and 20 address bits. The 11 most</div><div class="t m0 x2c h6 y13d ff3 fs1 fc0 sc0 lsf ws0">significant address bits (PA10-PA0) s elect the page in the</div><div class="t m0 x2c h6 y13e ff3 fs1 fc0 sc0 ls1 ws0">main memory where data is to be written, and the next nine</div><div class="t m0 x2c h6 y13f ff3 fs1 fc0 sc0 ls1 ws0">address bits (BFA8-BFA0) select the first byte in the buffer</div><div class="t m0 x2c h6 y140 ff3 fs1 fc0 sc0 ls35 ws0">to be wri tten. Afte r al l a ddre ss bits a re sh if ted in, th e part</div><div class="t m0 x2c h6 y141 ff3 fs1 fc0 sc0 ls22 ws0">will take data from the SI pin and store it in one of the data</div><div class="t m0 x2c h6 y142 ff3 fs1 fc0 sc0 lse ws0">buffers. If the e nd of th e b uff er i s reache d, the dev ic e will</div><div class="t m0 x2c h6 y143 ff3 fs1 fc0 sc0 ls25 ws0">wrap around back to the beginning of the b uffer. When</div><div class="t m0 x2c h6 y144 ff3 fs1 fc0 sc0 lsc ws0">there is a low to high transition on the CS</div><div class="t m0 x4d h6 y145 ff3 fs1 fc0 sc0 lsf ws0">pin, the part will</div><div class="t m0 x2c h6 y146 ff3 fs1 fc0 sc0 lsf ws0">first erase the selected p age in main memory to all 1s and</div><div class="t m0 x2c h6 y147 ff3 fs1 fc0 sc0 ls1 ws0">then program the data stored in the buffer into the specified</div><div class="t m0 x2c h6 y148 ff3 fs1 fc0 sc0 ls1 ws0">page in the main memory. Both the erase and the program-</div><div class="t m0 x2c h6 y149 ff3 fs1 fc0 sc0 lsf ws0">ming of the page are internally self timed and should take</div><div class="t m0 x2c h6 y14a ff3 fs1 fc0 sc0 lse ws0">place in a maximum of time t</div><div class="t m0 x4e h7 y14b ff3 fs4 fc0 sc0 ls3f ws0">EP</div><div class="t m0 x4f h6 y14c ff3 fs1 fc0 sc0 ls1 ws0">. During this time, the status</div><div class="t m0 x2c h6 y14d ff3 fs1 fc0 sc0 ls1 ws0">register will indicate that the part is busy.</div><div class="t m0 x2c h3 y14e ff1 fs1 fc0 sc0 ls40 ws0">AUTO P AGE REWRITE:</div><div class="t m0 x48 h6 y14f ff3 fs1 fc0 sc0 ls22 ws0">This mode is only needed if multi-</div><div class="t m0 x2c h6 y150 ff3 fs1 fc0 sc0 ls22 ws0">ple bytes within a page or multiple pages of data are modi-</div><div class="t m0 x2c h6 y151 ff3 fs1 fc0 sc0 ls22 ws0">fied in a random fashion. This mode is a combination of two</div><div class="t m0 x2c h6 y152 ff3 fs1 fc0 sc0 ls3c ws0">operations: Main Memory Page to Buffer Transfer and</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b7fc815da9b288b89274e/bg4.jpg"><div class="t m0 x28 h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">AT45DB041</div><div class="t m0 x3 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">4</div><div class="t m0 x3 h6 ycf ff3 fs1 fc0 sc0 lse ws0">Buffer to Mai n Memory Page Program with Built-In Erase.</div><div class="t m0 x3 h6 yd0 ff3 fs1 fc0 sc0 lsf ws0">A page of data is first transferred from the main memory to</div><div class="t m0 x3 h6 yd1 ff3 fs1 fc0 sc0 ls28 ws0">buffer 1 or buffer 2, and then the same data (from buffer 1</div><div class="t m0 x3 h6 yd2 ff3 fs1 fc0 sc0 lsd ws0">or bu ffer 2) i s program med ba ck into its origina l p age of</div><div class="t m0 x3 h6 yd3 ff3 fs1 fc0 sc0 ls1 ws0">main memory. An 8-bit opcode, 58H for buffer 1 or 59H for</div><div class="t m0 x3 h6 yd4 ff3 fs1 fc0 sc0 ls2a ws0">buffer 2, is followed by the four reserved bits, 11 address</div><div class="t m0 x3 h6 y153 ff3 fs1 fc0 sc0 lsf ws0">bits (P A10-PA 0) that spec if y the p ag e i n main mem or y to</div><div class="t m0 x3 h6 y154 ff3 fs1 fc0 sc0 lsd ws0">be rewritten, and nin e addi tional don't car e bits. When a</div><div class="t m0 x3 h6 y155 ff3 fs1 fc0 sc0 ls41 ws0">low to high transition occurs on the CS</div><div class="t m0 x50 h6 y156 ff3 fs1 fc0 sc0 ls22 ws0">pin, the part will first</div><div class="t m0 x3 h6 y157 ff3 fs1 fc0 sc0 ls22 ws0">transfer data from the page in main memory to a buffer and</div><div class="t m0 x3 h6 y158 ff3 fs1 fc0 sc0 ls22 ws0">then program the data from the buffer back into same page</div><div class="t m0 x3 h6 y159 ff3 fs1 fc0 sc0 lsf ws0">of main memory. The operation is internally self-timed and</div><div class="t m0 x3 h6 y15a ff3 fs1 fc0 sc0 ls2e ws0">should take place in a maximum time of t</div><div class="t m0 x51 h7 y11f ff3 fs4 fc0 sc0 ls34 ws0">EP</div><div class="t m0 x52 h6 y120 ff3 fs1 fc0 sc0 ls42 ws0">.Duringthis</div><div class="t m0 x3 h6 y121 ff3 fs1 fc0 sc0 ls1 ws0">time, the status register will indicate that the part is busy.</div><div class="t m0 x3 h6 y15b ff3 fs1 fc0 sc0 ls29 ws0">If the main memory is programmed or reprogrammed</div><div class="t m0 x3 h6 y124 ff3 fs1 fc0 sc0 ls27 ws0">sequentially page by page, then the programming algo-</div><div class="t m0 x3 h6 y125 ff3 fs1 fc0 sc0 ls25 ws0">rithm shown in F igure 1 i s recom mended. Ot herwise, if</div><div class="t m0 x3 h6 y126 ff3 fs1 fc0 sc0 ls1 ws0">multiple bytes in a page or several pages are programmed</div><div class="t m0 x3 h6 y127 ff3 fs1 fc0 sc0 ls1 ws0">randomly in the main memory, then the programming algo-</div><div class="t m0 x3 h6 y128 ff3 fs1 fc0 sc0 ls1 ws0">rithm shown in Figure 2 is recommended.</div><div class="t m0 x3 h3 y15c ff1 fs1 fc0 sc0 ls3d ws0">STATUS REGISTER:</div><div class="t m0 x19 h6 y15d ff3 fs1 fc0 sc0 ls43 ws0">Thestatusregistercanbeusedto</div><div class="t m0 x3 h6 y15e ff3 fs1 fc0 sc0 lsd ws0">determine the dev ice’s ready/busy status , the res ult of a</div><div class="t m0 x3 h6 y15f ff3 fs1 fc0 sc0 lsd ws0">Main Memory Page to Buffer C ompare operat ion , o r the</div><div class="t m0 x3 h6 y160 ff3 fs1 fc0 sc0 ls2a ws0">device density. To read the status register, an opcode of</div><div class="t m0 x3 h6 y161 ff3 fs1 fc0 sc0 ls22 ws0">57H must be loaded into the device. After the last bit of the</div><div class="t m0 x3 h6 y162 ff3 fs1 fc0 sc0 lsd ws0">opcode is shifte d in, th e e ight bi ts of th e s tatus regis ter,</div><div class="t m0 x3 h6 y163 ff3 fs1 fc0 sc0 lsf ws0">starting with the MSB (bit 7), will be shifted out on the SO</div><div class="t m0 x3 h6 y164 ff3 fs1 fc0 sc0 ls22 ws0">pin during the next eight clock cycles. The five most-signifi-</div><div class="t m0 x3 h6 y165 ff3 fs1 fc0 sc0 lse ws0">cant bits of the status register will contain dev ice inform a-</div><div class="t m0 x3 h6 y166 ff3 fs1 fc0 sc0 ls27 ws0">tion, while the remaining three least-significant bits are</div><div class="t m0 x3 h6 y167 ff3 fs1 fc0 sc0 ls27 ws0">reserved for future u se and will have undefined values.</div><div class="t m0 x3 h6 y168 ff3 fs1 fc0 sc0 ls2a ws0">After bit 0 of the status register has been shifted out, the</div><div class="t m0 x3 h6 y169 ff3 fs1 fc0 sc0 ls22 ws0">sequence will repeat itself (as long as CS</div><div class="t m0 x53 h6 yf8 ff3 fs1 fc0 sc0 ls22 ws0">remains low and</div><div class="t m0 x3 h6 yf9 ff3 fs1 fc0 sc0 lsf ws0">SCK is being toggled) starting again with bit 7. The data in</div><div class="t m0 x3 h6 yfa ff3 fs1 fc0 sc0 ls22 ws0">the status register is constantly updated, so each repeating</div><div class="t m0 x3 h6 y16a ff3 fs1 fc0 sc0 ls22 ws0">sequence will output new data.</div><div class="t m0 x3 h6 y16b ff3 fs1 fc0 sc0 ls22 ws0">Ready/busy status is indicated using bit 7 of the status reg-</div><div class="t m0 x3 h6 y16c ff3 fs1 fc0 sc0 lsf ws0">ister. If bit 7 is a 1, then the device is not busy and is ready</div><div class="t m0 x3 h6 y16d ff3 fs1 fc0 sc0 ls1 ws0">to accept the next command. If bit 7 is a 0, then the device</div><div class="t m0 x3 h6 y16e ff3 fs1 fc0 sc0 ls1 ws0">is in a busy state. The user can continuously poll bit 7 of the</div><div class="t m0 x3 h6 y16f ff3 fs1 fc0 sc0 ls1 ws0">status register by stopping SCK once bit 7 has been output.</div><div class="t m0 x3 h6 y170 ff3 fs1 fc0 sc0 ls1 ws0">The status of bit 7 will continue to be output on the SO pin,</div><div class="t m0 x3 h6 y171 ff3 fs1 fc0 sc0 ls1 ws0">and once the device is no longer busy, the state of SO will</div><div class="t m0 x3 h6 y172 ff3 fs1 fc0 sc0 ls27 ws0">change from 0 to 1. There are six operations which can</div><div class="t m0 x3 h6 y173 ff3 fs1 fc0 sc0 ls22 ws0">cause the device to be in a busy state: Main Memory Page</div><div class="t m0 x3 h6 y174 ff3 fs1 fc0 sc0 lse ws0">to Buffer Transfer, Main Memory Page to Buffer Compare,</div><div class="t m0 x3 h6 y175 ff3 fs1 fc0 sc0 lse ws0">Buffer to Mai n Memory Page Program with Built-In Erase,</div><div class="t m0 x3 h6 y176 ff3 fs1 fc0 sc0 ls3c ws0">Buffer to Main Memory Pa ge Pr ogram without Built-In</div><div class="t m0 x2c h6 y177 ff3 fs1 fc0 sc0 ls2f ws0">Erase, Main Memory Page Program, and Auto Page</div><div class="t m0 x2c h6 y178 ff3 fs1 fc0 sc0 ls14 ws0">Rewrite.</div><div class="t m0 x2c h6 y179 ff3 fs1 fc0 sc0 lsc ws0">The result of the most recent Main Memory Page to Buffer</div><div class="t m0 x2c h6 y17a ff3 fs1 fc0 sc0 ls27 ws0">Compare operation is indicated using bit 6 of the status</div><div class="t m0 x2c h6 y17b ff3 fs1 fc0 sc0 lsd ws0">register. If bit 6 is a 0, then the data in the main memory</div><div class="t m0 x2c h6 y17c ff3 fs1 fc0 sc0 lse ws0">page matches the data in t he buffer. If bit 6 is a 1, then at</div><div class="t m0 x2c h6 y17d ff3 fs1 fc0 sc0 ls1 ws0">least one bit of the data in the main memory page does not</div><div class="t m0 x2c h6 y17e ff3 fs1 fc0 sc0 ls1 ws0">match the data in the buffer.</div><div class="t m0 x2c h6 y17f ff3 fs1 fc0 sc0 ls1 ws0">The device density is indicated using bits 5, 4, and 3 of the</div><div class="t m0 x2c h6 y180 ff3 fs1 fc0 sc0 ls1 ws0">status register. For the AT45DB041, the three bits are 0, 1,</div><div class="t m0 x2c h6 y181 ff3 fs1 fc0 sc0 lse ws0">and 1. The deci mal value of th ese three bi na ry bits does</div><div class="t m0 x2c h6 y182 ff3 fs1 fc0 sc0 ls1 ws0">not equate to the device density; the three bits represent a</div><div class="t m0 x2c h6 y183 ff3 fs1 fc0 sc0 ls2a ws0">combinational code relating to differing densities of Serial</div><div class="t m0 x2c h6 y184 ff3 fs1 fc0 sc0 ls1 ws0">DataFlash devices, allowing a total of eight different density</div><div class="t m0 x2c h6 y185 ff3 fs1 fc0 sc0 ls1 ws0">configurations.</div><div class="t m0 x2c h10 y186 ff1 fsa fc0 sc0 ls14 ws0">Read/Program Mode Summary</div><div class="t m0 x2c h6 y187 ff3 fs1 fc0 sc0 ls44 ws0">Themodeslistedabovecanbeseparatedintotwogroups</div><div class="t m0 x2c h6 y188 ff3 fs1 fc0 sc0 ls45 ws0">— modes which make use of the flash memory array</div><div class="t m0 x2c h6 y189 ff3 fs1 fc0 sc0 lsf ws0">(Group A) an d mod es wh ich do not mak e use of the flash</div><div class="t m0 x2c h6 y18a ff3 fs1 fc0 sc0 ls1 ws0">memory array (Group B).</div><div class="t m0 x2c h6 y18b ff3 fs1 fc0 sc0 ls1 ws0">Group A modes consist of:</div><div class="t m0 x2c h6 y18c ff3 fs1 fc0 sc0 ls1 ws0">1. Main memory page read</div><div class="t m0 x2c h6 y18d ff3 fs1 fc0 sc0 ls1 ws0">2. Main memory page to buffer 1 (or 2) transfer</div><div class="t m0 x2c h6 y18e ff3 fs1 fc0 sc0 ls1 ws0">3. Main memory page to buffer 1 (or 2) compare</div><div class="t m0 x2c h6 y18f ff3 fs1 fc0 sc0 ls1 ws0">4. Buffer 1 (or 2) to main memory page program with</div><div class="t m0 x2d h6 y190 ff3 fs1 fc0 sc0 ls46 ws0">built-in erase</div><div class="t m0 x2c h6 y191 ff3 fs1 fc0 sc0 ls1 ws0">5. Buffer 1 (or 2) to main memory page program with-</div><div class="t m0 x2d h6 y192 ff3 fs1 fc0 sc0 ls1 ws0">out built-in erase</div><div class="t m0 x2c h6 y193 ff3 fs1 fc0 sc0 ls1 ws0">6. Main memory page program</div><div class="t m0 x2c h6 y194 ff3 fs1 fc0 sc0 ls28 ws0">7. Auto page rewrite</div><div class="t m0 x2c h6 y195 ff3 fs1 fc0 sc0 ls22 ws0">Group B modes consist of:</div><div class="t m0 x2c h6 y196 ff3 fs1 fc0 sc0 ls22 ws0">1. Buffer 1 (or 2) read</div><div class="t m0 x2c h6 y197 ff3 fs1 fc0 sc0 ls28 ws0">2. Buffer 1 (or 2) write</div><div class="t m0 x2c h6 y198 ff3 fs1 fc0 sc0 ls1 ws0">3. Status read</div><div class="t m0 x2c h6 y199 ff3 fs1 fc0 sc0 ls1 ws0">If a Group A mode is in progress (not fully completed) then</div><div class="t m0 x2c h6 y19a ff3 fs1 fc0 sc0 lsf ws0">another mode in Group A should not be started. However,</div><div class="t m0 x2c h6 y19b ff3 fs1 fc0 sc0 ls2a ws0">during this time in which a Group A mode is in progress,</div><div class="t m0 x2c h6 y19c ff3 fs1 fc0 sc0 ls22 ws0">modes in Group B can be started.</div><div class="t m0 x2c h6 y19d ff3 fs1 fc0 sc0 ls47 ws0">This gives the Serial DataFlash the ability to virtually</div><div class="t m0 x2c h6 y19e ff3 fs1 fc0 sc0 ls25 ws0">accomm odate a continu ous da ta stream . While data i s</div><div class="t m0 x2c h6 y19f ff3 fs1 fc0 sc0 ls2a ws0">being programmed into main memory from buffer 1, data</div><div class="t m0 x2c h6 y1a0 ff3 fs1 fc0 sc0 ls22 ws0">can be loaded into buffer 2 (or vice versa). See application</div><div class="t m0 x2c h6 y1a1 ff3 fs1 fc0 sc0 ls25 ws0">note AN-4 (“Using A tmel’s Serial DataFlash”) for more</div><div class="t m0 x2c h6 y1a2 ff3 fs1 fc0 sc0 ls1 ws0">details.</div><div class="t m0 x3 h4 y1a3 ff1 fs2 fc0 sc0 ls48 ws0">Status Register Format</div><div class="t m0 x1e h3 y1a4 ff1 fs1 fc0 sc0 ls14 ws0">Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0</div><div class="t m0 x54 h6 y1a5 ff3 fs1 fc0 sc0 ls28 ws0">RDY/BUSY</div><div class="t m0 x19 h6 y1a6 ff3 fs1 fc0 sc0 ls6 ws0">COMP 0 1 1 X X X</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>