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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259ee1cbe9ad24cfac9df2e/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Wind River Systems</div><div class="t m0 x2 h3 y2 ff2 fs0 fc0 sc0 ls0 ws0">T<span class="_ _0"></span>ornado Device Driver W<span class="_ _0"></span>orkshop<span class="_ _1"> </span>© Copyright W<span class="_ _2"></span>ind River Systems<span class="_ _3"> </span><span class="fs1">E</span>-<span class="fs1">1</span></div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">Appendix</div><div class="t m0 x4 h5 y4 ff3 fs3 fc0 sc0 ls0 ws0">E</div><div class="t m0 x5 h6 y5 ff3 fs4 fc0 sc0 ls0 ws0">VME Basics</div><div class="t m0 x6 h7 y6 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Intr<span class="_ _2"></span>oduction to the VMEbus</div><div class="t m0 x6 h7 y7 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Accessing boar<span class="_ _2"></span>ds across the VMEbus</div><div class="t m0 x6 h7 y8 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>VMEbus interrupt handling</div></div><div class="pi" data-data='{"ctm":[1.708185,0.000000,0.000000,1.708185,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259ee1cbe9ad24cfac9df2e/bg2.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Wind River Systems</div><div class="t m0 x2 h3 y2 ff2 fs0 fc0 sc0 ls0 ws0">T<span class="_ _0"></span>ornado Device Driver W<span class="_ _0"></span>orkshop<span class="_ _1"> </span>© Copyright W<span class="_ _2"></span>ind River Systems<span class="_ _3"> </span><span class="fs1">E</span>-<span class="fs1">2</span></div><div class="t m0 x7 h8 y9 ff3 fs6 fc0 sc0 ls0 ws0">VME Basics</div><div class="t m0 x8 h4 ya ff4 fs2 fc1 sc0 ls0 ws0">8.6<span class="_ _5"> </span>VMEbus Addressing</div><div class="t m0 x9 h9 yb ff5 fs2 fc0 sc0 ls0 ws0">VMEbus Interrupts</div><div class="t m0 x6 h7 y6 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>VMEbus addr<span class="_ _2"></span>ess spaces (Address Modifiers)</div><div class="t m0 x6 h7 y7 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>CPU memory maps</div><div class="t m0 x6 h7 y8 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Converting a VMEbus addr<span class="_ _2"></span>ess to a local address</div><div class="t m0 x6 h7 yc ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Cr<span class="_ _2"></span>eating a virtual to physical map to access (unmapped) VMEbus</div><div class="t m0 xa h7 yd ff2 fs5 fc0 sc0 ls0 ws0">addr<span class="_ _2"></span>ess</div></div><div class="pi" data-data='{"ctm":[1.708185,0.000000,0.000000,1.708185,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259ee1cbe9ad24cfac9df2e/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Wind River Systems</div><div class="t m0 x2 h3 y2 ff2 fs0 fc0 sc0 ls0 ws0">T<span class="_ _0"></span>ornado Device Driver W<span class="_ _0"></span>orkshop<span class="_ _1"> </span>© Copyright W<span class="_ _2"></span>ind River Systems<span class="_ _3"> </span><span class="fs1">E</span>-<span class="fs1">3</span></div><div class="t m0 xb h8 y9 ff3 fs6 fc0 sc0 ls0 ws0">VMEbus T<span class="_ _6"></span>er<span class="_ _7"></span>minology</div><div class="t m0 xc h7 ye ff2 fs5 fc0 sc0 ls0 ws0">Master<span class="_ _8"> </span>A boar<span class="_ _2"></span>d which can initiate data transfer</div><div class="t m0 xc h7 yf ff2 fs5 fc0 sc0 ls0 ws0">Slave<span class="_ _9"> </span>A boar<span class="_ _2"></span>d which responds to r<span class="_ _2"></span>equests</div><div class="t m0 xd h7 y10 ff2 fs5 fc0 sc0 ls0 ws0">generated by a master</div><div class="t m0 xc h7 y11 ff2 fs5 fc0 sc0 ls0 ws0">Arbiter<span class="_ _a"> </span>A boar<span class="_ _2"></span>d that grants masters control of</div><div class="t m0 xd h7 y12 ff2 fs5 fc0 sc0 ls0 ws0">the bus</div><div class="t m0 xe h7 y13 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Only the system contr<span class="_ _2"></span>oller in the first slot can be the</div><div class="t m0 xc h7 y14 ff2 fs5 fc0 sc0 ls0 ws0">arbiter<span class="_ _6"></span>.</div><div class="t m0 xe h7 y15 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Most I/O boar<span class="_ _2"></span>ds are slaves.</div><div class="t m0 xe h7 y16 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Some I/O boar<span class="_ _2"></span>ds are masters. Most masters ar<span class="_ _2"></span>e also</div><div class="t m0 xc h7 y17 ff2 fs5 fc0 sc0 ls0 ws0">slaves.</div><div class="t m0 x6 h7 y6 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>VMEbus is called a “multimaster bus,” since multiple boar<span class="_ _2"></span>ds may</div><div class="t m0 xa h7 y18 ff2 fs5 fc0 sc0 ls0 ws0">initiate data transfers.</div><div class="t m0 x6 h7 y19 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Whether a boar<span class="_ _2"></span>d can be a master<span class="_ _6"></span>, slave, or arbiter is hardwar<span class="_ _2"></span>e</div><div class="t m0 xa h7 y1a ff2 fs5 fc0 sc0 ls0 ws0">determined.</div><div class="t m0 xa ha y1b ff6 fs7 fc2 sc0 ls0 ws0">The Matrix DAADIO is an example of a slave<span class="_ _0"></span>. CPU cards are typically masters and slaves<span class="_ _0"></span>. I/O boards with</div><div class="t m0 xa ha y1c ff6 fs7 fc2 sc0 ls0 ws0">microprocessors on-board may be masters<span class="_ _0"></span>. The Matrix MS-SCSIFD (SCSI & floppy controller) is an example of an</div><div class="t m0 xa ha y1d ff6 fs7 fc2 sc0 ls0 ws0">I/O master<span class="_ _6"></span>.Since most I/O boards are slaves only<span class="_ _0"></span>, the driver writer needs to know how the master (CPU card)</div><div class="t m0 xa ha y1e ff6 fs7 fc2 sc0 ls0 ws0">accesses the I/O board, but does not have to concern themselves with the I/O board accessing the master (since it</div><div class="t m0 xa ha y1f ff6 fs7 fc2 sc0 ls0 ws0">only responds to the master’<span class="_ _2"></span>s requests). If the I/O board is also a master<span class="_ _6"></span>, then the driver needs to be aware how</div><div class="t m0 xa ha y20 ff6 fs7 fc2 sc0 ls0 ws0">access can be made in both directions<span class="_ _0"></span>.Note that while most masters are slaves<span class="_ _2"></span>, not all slaves are masters<span class="_ _2"></span>.</div></div><div class="pi" data-data='{"ctm":[1.708185,0.000000,0.000000,1.708185,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259ee1cbe9ad24cfac9df2e/bg4.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Wind River Systems</div><div class="t m0 x2 h3 y2 ff2 fs0 fc0 sc0 ls0 ws0">T<span class="_ _0"></span>ornado Device Driver W<span class="_ _0"></span>orkshop<span class="_ _1"> </span>© Copyright W<span class="_ _2"></span>ind River Systems<span class="_ _3"> </span><span class="fs1">E</span>-<span class="fs1">4</span></div><div class="t m0 xf h8 y9 ff3 fs6 fc0 sc0 ls0 ws0">VME Bac<span class="_ _2"></span>kplane</div><div class="t m0 xe h7 y21 ff2 fs5 fc0 sc0 ls0 ws0">The VMEbus is designed for flexibility to accommodate</div><div class="t m0 xe h7 y22 ff2 fs5 fc0 sc0 ls0 ws0">varying needs:</div><div class="t m0 x10 h7 y23 ff2 fs5 fc0 sc0 ls0 ws0">P1/J1<span class="_ _b"> </span>24 bit addr<span class="_ _2"></span>essing, 16 bit data, plus</div><div class="t m0 x11 h7 y24 ff2 fs5 fc0 sc0 ls0 ws0">contr<span class="_ _2"></span>ol lines</div><div class="t m0 x10 h7 y25 ff2 fs5 fc0 sc0 ls0 ws0">P2/J2<span class="_ _b"> </span>Expands capability to 32 bit addr<span class="_ _2"></span>essing</div><div class="t m0 x11 h7 y26 ff2 fs5 fc0 sc0 ls0 ws0">and 32 bit data</div><div class="t m0 x12 h7 y27 ff2 fs5 fc0 sc0 ls0 ws0"> VME Chassis</div><div class="t m0 x13 h7 y28 ff2 fs5 fc0 sc0 ls0 ws0">P1</div><div class="t m0 x14 h7 y29 ff2 fs5 fc0 sc0 ls0 ws0">P2</div><div class="t m0 x15 h7 y2a ff2 fs5 fc0 sc0 ls0 ws0">backplane</div><div class="t m0 x15 h7 y2b ff2 fs5 fc0 sc0 ls0 ws0">connectors</div><div class="t m0 x6 h7 y6 ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>The most common car<span class="_ _2"></span>ds are double height (6U), which connect into</div><div class="t m0 xa h7 y18 ff2 fs5 fc0 sc0 ls0 ws0">both P1 and P2.</div><div class="t m0 x6 h7 y2c ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Single height (3U) car<span class="_ _2"></span>ds are also common.</div><div class="t m0 x6 h7 y2d ff2 fs5 fc0 sc0 ls0 ws0">•<span class="_ _4"> </span>Do NOT leave empty slots between boar<span class="_ _2"></span>ds (unless the backplane is</div><div class="t m0 xa h7 y2e ff2 fs5 fc0 sc0 ls0 ws0">corr<span class="_ _2"></span>ectly jumpered for it).</div><div class="t m0 xa ha y2f ff6 fs7 fc2 sc0 ls0 ws0">The Matrix DAADIO is an example of a slave<span class="_ _0"></span>. CPU cards are typically masters and slaves<span class="_ _0"></span>. I/O boards with</div><div class="t m0 xa ha y30 ff6 fs7 fc2 sc0 ls0 ws0">microprocessors on-board may be masters<span class="_ _0"></span>. The Matrix MS-SCSIFD (SCSI & floppy controller) is an example of an</div><div class="t m0 xa ha y31 ff6 fs7 fc2 sc0 ls0 ws0">I/O master<span class="_ _6"></span>.Since most I/O boards are slaves only<span class="_ _0"></span>, the driver writer needs to know how the master (CPU card)</div><div class="t m0 xa ha y32 ff6 fs7 fc2 sc0 ls0 ws0">accesses the I/O board, but does not have to concern themselves with the I/O board accessing the master (since it</div><div class="t m0 xa ha y33 ff6 fs7 fc2 sc0 ls0 ws0">only responds to the master’<span class="_ _2"></span>s requests). If the I/O board is also a master<span class="_ _6"></span>, then the driver needs to be aware how</div><div class="t m0 xa ha y34 ff6 fs7 fc2 sc0 ls0 ws0">access can be made in both directions<span class="_ _0"></span>. Note that while most masters are slaves<span class="_ _2"></span>, not all slaves are masters<span class="_ _2"></span>.</div></div><div class="pi" data-data='{"ctm":[1.708185,0.000000,0.000000,1.708185,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259ee1cbe9ad24cfac9df2e/bg5.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Wind River Systems</div><div class="t m0 x2 h3 y2 ff2 fs0 fc0 sc0 ls0 ws0">T<span class="_ _0"></span>ornado Device Driver W<span class="_ _0"></span>orkshop<span class="_ _1"> </span>© Copyright W<span class="_ _2"></span>ind River Systems<span class="_ _3"> </span><span class="fs1">E</span>-<span class="fs1">5</span></div><div class="t m0 x16 h8 y9 ff3 fs6 fc0 sc0 ls0 ws0">VMEbus Address Spaces</div><div class="t m0 x17 hb y35 ff7 fs5 fc0 sc0 ls0 ws0">Name</div><div class="t m0 x18 hc y36 ff8 fs5 fc0 sc0 ls0 ws0"> Address</div><div class="t m0 x19 hc y37 ff8 fs5 fc0 sc0 ls0 ws0">Length</div><div class="t m0 x1a hc y35 ff8 fs5 fc0 sc0 ls0 ws0">Size</div><div class="t m0 x1b hd y38 ff9 fs8 fc0 sc0 ls0 ws0">Short I/O</div><div class="t m0 x1b hd y39 ff9 fs8 fc0 sc0 ls0 ws0">(A16)</div><div class="t m0 x1c he y3a ff2 fs8 fc0 sc0 ls0 ws0">16-bit<span class="_ _c"> </span>64 Kbytes</div><div class="t m0 x1b hd y3b ff9 fs8 fc0 sc0 ls0 ws0">Standard</div><div class="t m0 x1b hd y3c ff9 fs8 fc0 sc0 ls0 ws0">(A24)</div><div class="t m0 x1d hd y3d ff9 fs8 fc0 sc0 ls0 ws0">24-bit<span class="_ _d"> </span>16 Mbytes</div><div class="t m0 x1b hd y3e ff9 fs8 fc0 sc0 ls0 ws0">Extended</div><div class="t m0 x1b hd y3f ff9 fs8 fc0 sc0 ls0 ws0">(A32)</div><div class="t m0 x1d hd y40 ff9 fs8 fc0 sc0 ls0 ws0">32-bit<span class="_ _e"> </span>4 Gbytes</div><div class="t m0 xa ha y41 ff6 fs7 fc2 sc0 ls0 ws0">The VMEbus was designed with these different addressing modes to permit a wide range of applications: less</div><div class="t m0 xa ha y42 ff6 fs7 fc2 sc0 ls0 ws0">demanding applications can use Short I/O (A16) addressing which requires less hardware (e<span class="_ _0"></span>.g<span class="_ _2"></span>. address decoding</div><div class="t m0 xa ha y43 ff6 fs7 fc2 sc0 ls0 ws0">logic) while more complex applications can use the full 32-bit addressing<span class="_ _0"></span>.</div></div><div class="pi" data-data='{"ctm":[1.708185,0.000000,0.000000,1.708185,0.000000,0.000000]}'></div></div>
