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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b6b1c15da9b288ba52e98/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">VLSI</div><div class="t m0 x1 h3 y3 ff1 fs0 fc0 sc0 ls0 ws0">Design</div><div class="t m0 x1 h4 y4 ff1 fs1 fc1 sc0 ls0 ws0">CMOS <span class="_ _0"></span>T<span class="_ _1"></span>ransistor <span class="_ _0"></span>Theory</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b6b1c15da9b288ba52e98/bg2.jpg"><div class="c x0 y5 w3 h5"><div class="t m0 x2 h6 y6 ff2 fs2 fc2 sc0 ls0 ws0">3: CMOS <span class="_ _2"></span>T<span class="_ _2"></span>ransistor <span class="_ _2"></span>Theory<span class="_ _3"> </span>2</div><div class="t m0 x3 h7 y7 ff3 fs3 fc1 sc0 ls0 ws0">EE 447 VLSI <span class="_ _4"></span>Design</div></div><div class="c x0 y1 w2 h2"><div class="t m0 x4 h8 y8 ff1 fs4 fc0 sc0 ls0 ws0">Outline</div><div class="t m0 x4 h9 y9 ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha ya ff2 fs6 fc2 sc0 ls0 ws0">Introduction</div><div class="t m0 x4 h9 yb ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha yc ff2 fs6 fc2 sc0 ls0 ws0">MOS Capacitor</div><div class="t m0 x4 h9 yd ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha ye ff2 fs6 fc2 sc0 ls0 ws0">nMOS I-V Characteristics</div><div class="t m0 x4 h9 yf ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha y10 ff2 fs6 fc2 sc0 ls0 ws0">pMOS I-V Characteristics</div><div class="t m0 x4 h9 y11 ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha y12 ff2 fs6 fc2 sc0 ls0 ws0">Gate and Diffusion Capacitance</div><div class="t m0 x4 h9 y13 ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha y14 ff2 fs6 fc2 sc0 ls0 ws0">Pass Transistors</div><div class="t m0 x4 h9 y15 ff4 fs5 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 ha y16 ff2 fs6 fc2 sc0 ls0 ws0">RC Delay Models</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b6b1c15da9b288ba52e98/bg3.jpg"><div class="c x0 y5 w3 h5"><div class="t m0 x2 h6 y6 ff2 fs2 fc2 sc0 ls0 ws0">3: CMOS <span class="_ _2"></span>T<span class="_ _2"></span>ransistor <span class="_ _2"></span>Theory<span class="_ _3"> </span>3</div><div class="t m0 x3 h7 y7 ff3 fs3 fc1 sc0 ls0 ws0">EE 447 VLSI <span class="_ _4"></span>Design</div></div><div class="c x0 y1 w2 h2"><div class="t m0 x4 h8 y8 ff1 fs4 fc0 sc0 ls0 ws0">Introduction</div><div class="t m0 x4 hb y17 ff4 fs7 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 hc y18 ff2 fs8 fc2 sc0 ls0 ws0">So far, we have trea<span class="_ _4"></span>ted transistors as ide<span class="_ _4"></span>al switches</div><div class="t m0 x4 hb y19 ff4 fs7 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 hc y1a ff2 fs8 fc2 sc0 ls0 ws0">An ON transis<span class="_ _4"></span>tor passes a finite amoun<span class="_ _4"></span>t of current</div><div class="t m0 x6 hd y1b ff4 fs9 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 hc y1c ff2 fs8 fc2 sc0 ls0 ws0">Depends<span class="_ _4"></span> on terminal voltages</div><div class="t m0 x6 hd y1d ff4 fs9 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 hc y1e ff2 fs8 fc2 sc0 ls0 ws0">Derive cu<span class="_ _4"></span>rrent-voltage (I-<span class="_ _4"></span>V) relationships</div><div class="t m0 x4 hb y1f ff4 fs7 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 hc y20 ff2 fs8 fc2 sc0 ls0 ws0">Transistor<span class="_ _4"></span> gate, source, dra<span class="_ _4"></span>in all have capacitanc<span class="_ _4"></span>e</div><div class="t m0 x6 hd y21 ff4 fs9 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 he y22 ff2 fs8 fc2 sc0 ls0 ws0">I = C (<span class="ff4"></span>V/<span class="ff4"></span>t) -> <span class="ff4"><span class="_ _4"></span></span>t = (C/I) <span class="ff4"></span>V</div><div class="t m0 x6 hd y23 ff4 fs9 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 hc y24 ff2 fs8 fc2 sc0 ls0 ws0">Capacitanc<span class="_ _4"></span>e and current deter<span class="_ _4"></span>mine speed</div><div class="t m0 x4 hb y25 ff4 fs7 fc3 sc0 ls0 ws0"></div><div class="t m0 x5 hc y26 ff2 fs8 fc2 sc0 ls0 ws0">Also explore<span class="_ _4"></span> what a “degraded lev<span class="_ _4"></span>el” really means</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b6b1c15da9b288ba52e98/bg4.jpg"><div class="c x0 y5 w3 h5"><div class="t m0 x2 h6 y6 ff2 fs2 fc2 sc0 ls0 ws0">3: CMOS <span class="_ _2"></span>T<span class="_ _2"></span>ransistor <span class="_ _2"></span>Theory<span class="_ _3"> </span>4</div><div class="t m0 x3 h7 y7 ff3 fs3 fc1 sc0 ls0 ws0">EE 447 VLSI <span class="_ _4"></span>Design</div></div><div class="c x0 y1 w2 h2"><div class="t m0 x4 h8 y8 ff1 fs4 fc0 sc0 ls0 ws0">MOS Capacitor</div><div class="t m0 x4 hf y27 ff4 fsa fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h10 y28 ff2 fsb fc2 sc0 ls0 ws0">Gate and body form MOS capacitor</div><div class="t m0 x4 hf y29 ff4 fsa fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h10 y2a ff2 fsb fc2 sc0 ls0 ws0">Operating modes</div><div class="t m0 x6 hb y2b ff4 fs7 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 h10 y2c ff2 fsb fc2 sc0 ls0 ws0">Accumulation</div><div class="t m0 x6 hb y2d ff4 fs7 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 h10 y2e ff2 fsb fc2 sc0 ls0 ws0">Depletion</div><div class="t m0 x6 hb y2f ff4 fs7 fc4 sc0 ls0 ws0"></div><div class="t m0 x7 h10 y30 ff2 fsb fc2 sc0 ls0 ws0">Inversion</div><div class="t m0 x8 h11 y31 ff2 fsc fc2 sc0 ls0 ws0">polysilicon gate</div><div class="t m0 x9 h11 y32 ff2 fsc fc2 sc0 ls0 ws0">(a)</div><div class="t m0 x8 h11 y33 ff2 fsc fc2 sc0 ls0 ws0">silicon dioxide<span class="_ _2"></span> insulator</div><div class="t m0 x8 h11 y34 ff2 fsc fc2 sc0 ls0 ws0">p-type bod<span class="_ _2"></span>y</div><div class="t m0 xa h11 y35 ff2 fsc fc2 sc0 ls0 ws0">+</div><div class="t m0 xb h11 y36 ff2 fsc fc2 sc0 ls0 ws0">-</div><div class="t m0 xc h11 y37 ff2 fsc fc2 sc0 ls0 ws0">V</div><div class="t m0 xd h12 y38 ff2 fsd fc2 sc0 ls0 ws0">g</div><div class="t m0 xe h11 y37 ff2 fsc fc2 sc0 ls0 ws0"> < 0</div><div class="t m0 x9 h11 y39 ff2 fsc fc2 sc0 ls0 ws0">(b)</div><div class="t m0 xa h11 y3a ff2 fsc fc2 sc0 ls0 ws0">+</div><div class="t m0 xb h11 y3b ff2 fsc fc2 sc0 ls0 ws0">-</div><div class="t m0 xf h11 y3c ff2 fsc fc2 sc0 ls0 ws0">0 < V</div><div class="t m0 x10 h12 y3d ff2 fsd fc2 sc0 ls0 ws0">g</div><div class="t m0 x11 h11 y3c ff2 fsc fc2 sc0 ls0 ws0"> < V</div><div class="t m0 x12 h12 y3d ff2 fsd fc2 sc0 ls0 ws0">t</div><div class="t m0 x8 h11 y3e ff2 fsc fc2 sc0 ls0 ws0">depletion regio<span class="_ _2"></span>n</div><div class="t m0 x9 h11 y3f ff2 fsc fc2 sc0 ls0 ws0">(c)</div><div class="t m0 xa h11 y40 ff2 fsc fc2 sc0 ls0 ws0">+</div><div class="t m0 xb h11 y41 ff2 fsc fc2 sc0 ls0 ws0">-</div><div class="t m0 x13 h11 y42 ff2 fsc fc2 sc0 ls0 ws0">V</div><div class="t m0 x14 h12 y43 ff2 fsd fc2 sc0 ls0 ws0">g</div><div class="t m0 x10 h11 y42 ff2 fsc fc2 sc0 ls0 ws0"> > V</div><div class="t m0 x15 h12 y43 ff2 fsd fc2 sc0 ls0 ws0">t</div><div class="t m0 x8 h11 y44 ff2 fsc fc2 sc0 ls0 ws0">depletion regio<span class="_ _2"></span>n</div><div class="t m0 x8 h13 y45 ff2 fsc fc2 sc0 ls0 ws0">inversion regi<span class="_ _2"></span>on<span class="_ _5"></span><span class="fse">Example with an NMOS</span></div><div class="t m0 x16 h13 y46 ff2 fse fc2 sc0 ls0 ws0">capacitor</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b6b1c15da9b288ba52e98/bg5.jpg"><div class="c x0 y5 w3 h5"><div class="t m0 x2 h6 y6 ff2 fs2 fc2 sc0 ls0 ws0">3: CMOS <span class="_ _2"></span>T<span class="_ _2"></span>ransistor <span class="_ _2"></span>Theory<span class="_ _3"> </span>5</div><div class="t m0 x3 h7 y7 ff3 fs3 fc1 sc0 ls0 ws0">EE 447 VLSI <span class="_ _4"></span>Design</div></div><div class="c x0 y1 w2 h2"><div class="t m0 x4 h8 y8 ff1 fs4 fc0 sc0 ls0 ws0">Terminal Voltages</div><div class="t m0 x4 h14 y47 ff4 fsf fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h15 y48 ff2 fs10 fc2 sc0 ls0 ws0">Mode of operation depends on V</div><div class="t m0 xb h16 y49 ff2 fs11 fc2 sc0 ls0 ws0">g</div><div class="t m0 x17 h15 y48 ff2 fs10 fc2 sc0 ls0 ws0">, V</div><div class="t m0 x18 h16 y49 ff2 fs11 fc2 sc0 ls0 ws0">d</div><div class="t m0 x19 h15 y48 ff2 fs10 fc2 sc0 ls0 ws0">, V</div><div class="t m0 x1a h16 y49 ff2 fs11 fc2 sc0 ls0 ws0">s</div><div class="t m0 x1b h17 y4a ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h15 y4b ff2 fs10 fc2 sc0 ls0 ws0">V</div><div class="t m0 x1d h16 y4c ff2 fs11 fc2 sc0 ls0 ws0">gs</div><div class="t m0 x1e h15 y4b ff2 fs10 fc2 sc0 ls0 ws0"> = V</div><div class="t m0 x1f h16 y4c ff2 fs11 fc2 sc0 ls0 ws0">g</div><div class="t m0 x20 h15 y4b ff2 fs10 fc2 sc0 ls0 ws0"> – V</div><div class="t m0 x21 h16 y4c ff2 fs11 fc2 sc0 ls0 ws0">s</div><div class="t m0 x1b h17 y4d ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h15 y4e ff2 fs10 fc2 sc0 ls0 ws0">V</div><div class="t m0 x1d h16 y4f ff2 fs11 fc2 sc0 ls0 ws0">gd</div><div class="t m0 x1e h15 y4e ff2 fs10 fc2 sc0 ls0 ws0"> = V</div><div class="t m0 x1f h16 y4f ff2 fs11 fc2 sc0 ls0 ws0">g</div><div class="t m0 x20 h15 y4e ff2 fs10 fc2 sc0 ls0 ws0"> – V</div><div class="t m0 x21 h16 y4f ff2 fs11 fc2 sc0 ls0 ws0">d</div><div class="t m0 x1b h17 y50 ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h15 y51 ff2 fs10 fc2 sc0 ls0 ws0">V</div><div class="t m0 x1d h16 y52 ff2 fs11 fc2 sc0 ls0 ws0">ds</div><div class="t m0 x1e h15 y51 ff2 fs10 fc2 sc0 ls0 ws0"> = V</div><div class="t m0 x1f h16 y52 ff2 fs11 fc2 sc0 ls0 ws0">d</div><div class="t m0 x20 h15 y51 ff2 fs10 fc2 sc0 ls0 ws0"> – V</div><div class="t m0 x21 h16 y52 ff2 fs11 fc2 sc0 ls0 ws0">s</div><div class="t m0 x22 h15 y51 ff2 fs10 fc2 sc0 ls0 ws0"> = V</div><div class="t m0 x23 h16 y52 ff2 fs11 fc2 sc0 ls0 ws0">gs</div><div class="t m0 x24 h15 y51 ff2 fs10 fc2 sc0 ls0 ws0"> - V</div><div class="t m0 x25 h16 y52 ff2 fs11 fc2 sc0 ls0 ws0">gd</div><div class="t m0 x4 h14 y53 ff4 fsf fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h15 y54 ff2 fs10 fc2 sc0 ls0 ws0">Source and drain are symmetric diffusion ter<span class="_ _2"></span>minals</div><div class="t m0 x1b h17 y55 ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h15 y56 ff2 fs10 fc2 sc0 ls0 ws0">However, V</div><div class="t m0 x21 h16 y57 ff2 fs11 fc2 sc0 ls0 ws0">ds</div><div class="t m0 x26 h18 y56 ff2 fs10 fc2 sc0 ls0 ws0"> <span class="ff4"></span> 0</div><div class="t m0 x4 h14 y58 ff4 fsf fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h15 y59 ff2 fs10 fc2 sc0 ls0 ws0">NMOS body is grounded. First assume source may be grounded </div><div class="t m0 x5 h15 y5a ff2 fs10 fc2 sc0 ls0 ws0">or may be at a voltage above ground.</div><div class="t m0 x4 h14 y5b ff4 fsf fc3 sc0 ls0 ws0"></div><div class="t m0 x5 h15 y5c ff2 fs10 fc2 sc0 ls0 ws0">Three regions of operation</div><div class="t m0 x1b h17 y5d ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h19 y43 ff5 fs10 fc2 sc0 ls0 ws0">Cutoff</div><div class="t m0 x1b h17 y5e ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h19 y5f ff5 fs10 fc2 sc0 ls0 ws0">Linear</div><div class="t m0 x1b h17 y60 ff4 fs12 fc4 sc0 ls0 ws0"></div><div class="t m0 x1c h19 y61 ff5 fs10 fc2 sc0 ls0 ws0">Saturation</div><div class="t m0 x27 h1a y62 ff2 fs13 fc1 sc0 ls0 ws0">V</div><div class="t m0 x28 h1b y63 ff2 fs14 fc1 sc0 ls0 ws0">g</div><div class="t m0 x29 h1a y64 ff2 fs13 fc1 sc0 ls0 ws0">V</div><div class="t m0 x2a h1b y65 ff2 fs14 fc1 sc0 ls0 ws0">s</div><div class="t m0 x2b h1a y64 ff2 fs13 fc1 sc0 ls0 ws0">V</div><div class="t m0 x2c h1b y65 ff2 fs14 fc1 sc0 ls0 ws0">d</div><div class="t m0 x2d h1a y66 ff2 fs13 fc2 sc0 ls0 ws0">V</div><div class="t m0 x2e h1b y67 ff2 fs14 fc2 sc0 ls0 ws0">gd</div><div class="t m0 x2f h1a y66 ff2 fs13 fc2 sc0 ls0 ws0">V</div><div class="t m0 x30 h1b y67 ff2 fs14 fc2 sc0 ls0 ws0">gs</div><div class="t m0 x31 h1a y68 ff2 fs13 fc2 sc0 ls0 ws0">V</div><div class="t m0 x32 h1b y51 ff2 fs14 fc2 sc0 ls0 ws0">ds</div><div class="t m0 x33 h1a y69 ff2 fs13 fc2 sc0 ls0 ws0">+</div><div class="t m0 x34 h1a y6a ff2 fs13 fc2 sc0 ls0 ws0">-</div><div class="t m0 x35 h1a y6b ff2 fs13 fc2 sc0 ls0 ws0">+</div><div class="t m0 x36 h1a y6c ff2 fs13 fc2 sc0 ls0 ws0">-</div><div class="t m0 x37 h1a y6d ff2 fs13 fc2 sc0 ls0 ws0">+</div><div class="t m0 x2b h1a y6c ff2 fs13 fc2 sc0 ls0 ws0">-</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
