BaiThiNghiem_3.zip

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openjpeg2000 >Source code for JPEG2000 by C langugue
BaiThiNghiem_3.zip
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  • sosanh_3bit.vhd
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  • lab_6_fsm.doc
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  • lab_4_comperator.doc
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/63803da0e53e5839a7e61866/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/63803da0e53e5839a7e61866/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Khoa <span class="ff2 ls1">&#272;<span class="ff1">i</span>&#7879;</span><span class="ls2 ws1">n t</span><span class="ff2 ls1">&#7917;<span class="ff1">-Vi</span>&#7877;</span><span class="ls3 ws2">n th&#244;ng, </span><span class="ff2 ls4">&#272;&#7841;</span><span class="ls5 ws3">i h</span><span class="ff2 ls1">&#7885;</span><span class="ls6 ws4">c B&#225;ch khoa H&#224; n</span><span class="ff2 ls1">&#7897;<span class="ff1">i<span class="ff3 fs1">&#58883;</span></span></span></div><div class="t m0 x2 h3 y2 ff1 fs0 fc0 sc0 ls4 ws0">Ng<span class="ff2 ls7">&#432;&#7901;</span><span class="ls8 ws5">i bi&#234;n so</span><span class="ff2 ls1">&#7841;</span><span class="ls9 ws6">n: KS. Nguy</span><span class="ff2 ls1">&#7877;</span><span class="ls0">n Minh Ti<span class="ff2 ls1">&#7871;</span><span class="ls9 ws6">n v&#224; TS. Ho&#224;ng M</span><span class="ff2 ls1">&#7841;</span><span class="lsa ws7">nh Th</span><span class="ff2 ls1">&#7855;</span><span class="ls2">ng <span class="ff3 lsb">&#58883;&#58883;<span class="_ _0"></span>1<span class="_ _1"></span>&#58883;</span></span></span></div><div class="t m0 x3 h4 y3 ff4 fs2 fc0 sc0 ls1 ws8">B&#192;I 3<span class="lsc ws0">: </span></div><div class="t m0 x4 h5 y4 ff4 fs2 fc0 sc0 lsd ws0">GI<span class="ff5 ls1">&#7898;</span><span class="lse ws9">I THI</span><span class="ff5 ls1">&#7878;</span><span class="lsf wsa">U V</span><span class="ff5 ls1">&#7872;</span><span class="ls10 wsb"> QUARTUS II V&#192; QUY TR&#204;NH THI</span><span class="ff5 ls1">&#7870;<span class="_ _2"></span></span><span class="ls11 wsc">T K</span><span class="ff5 ls1">&#7870;</span><span class="ls12 wsd"> TR&#202;N FPGA </span></div><div class="t m0 x3 h6 y5 ff4 fs0 fc0 sc0 ls7 ws0">1.<span class="ff6 ls1"> <span class="_ _3"> </span><span class="ff4">M<span class="ff5">&#7909;</span><span class="ls13 wse">c ti&#234;u</span> </span></span></div><div class="t m0 x3 h7 y6 ff7 fs0 fc0 sc0 ls14 ws0">B&#224;i th&#237; nghi<span class="ff8 ls1">&#7879;</span><span class="ls15 wsf">m n&#224;y gi</span><span class="ff8 ls1">&#7899;<span class="ff7 ws10">i thi</span>&#7879;</span><span class="ls7 ws11">u v</span><span class="ff8 ls1">&#7873;</span><span class="ls16 ws5"> ph</span><span class="ff8 ls1">&#7847;</span><span class="ls7 ws11">n m</span><span class="ff8 ls1">&#7873;</span><span class="ls17 ws12">m Quartus II v&#224; t</span><span class="ff8 ls1">&#7893;</span><span class="ls18 ws13">ng quan v</span><span class="ff8 ls1">&#7873;</span><span class="ls19 ws14"> c&#225;c b</span><span class="ff8 ls1a">&#432;&#7899;</span><span class="ls1b ws15">c th</span><span class="ff8 ls1">&#7921;</span><span class="ls17 ws12">c hi</span><span class="ff8 ls1">&#7879;</span><span class="ls1c ws16">n tr&#234;n CAD cho quy </span></div><div class="t m0 x3 h7 y7 ff7 fs0 fc0 sc0 ls1d ws17">tr&#236;nh thi<span class="ff8 ls1 ws0">&#7871;</span><span class="ls0 ws18">t k<span class="ff8 ls1 ws0">&#7871;<span class="ff7 ls1e"> m<span class="_ _4"></span><span class="ff8 ls1">&#7841;<span class="ff7 ls17 ws19">ch s</span>&#7889;<span class="ff7 ls1f ws1a">. V&#237; d</span>&#7909;<span class="ff7 ls1e"> v</span>&#7873;<span class="ff7 ls8 ws1b"> thi<span class="_ _4"></span><span class="ff8 ls1 ws0">&#7871;<span class="ff7 ls0 ws18">t k</span>&#7871;<span class="ff7 ls1e"> m</span>&#7841;<span class="ff7 ls17">ch </span><span class="ls7">&#273;&#417;<span class="ff7 ws1c">n gi</span></span>&#7843;<span class="ff7 ls7 ws1c">n minh h</span>&#7885;<span class="ff7 ls17 ws19">a cho t</span>&#7915;<span class="ff7 ls7 ws1c">ng b</span><span class="ls1a">&#432;&#7899;<span class="ff7 ls8 ws1b">c d&#249;ng ph</span></span>&#7847;<span class="ff7 ls7 ws1d">n m</span>&#7873;<span class="ff7 ls1c ws1e">m Quartus <span class="_ _4"></span>II </span></span></span></span></span></span></span></div><div class="t m0 x3 h7 y8 ff7 fs0 fc0 sc0 ls0 ws1f">v&#224; th<span class="ff8 ls1 ws0">&#7921;</span><span class="ls17 ws12">c hi<span class="ff8 ls1 ws0">&#7879;</span><span class="ls20 ws20">n tr&#234;n FPGA c<span class="ff8 ls1 ws0">&#7911;</span><span class="ls21 ws21">a Altera. </span></span></span></div><div class="t m0 x3 h6 y9 ff4 fs0 fc0 sc0 ls7 ws0">2.<span class="ff6 ls1"> <span class="_ _3"> </span></span><span class="ls22">Ki<span class="ff5 ls1">&#7871;</span><span class="ls17 ws12">n th</span><span class="ff5 ls1">&#7913;</span><span class="ls23 ws22">c c</span><span class="ff5 ls1">&#7847;</span><span class="ls14">n trang b<span class="ff5 ls1">&#7883;</span></span></span></div><div class="t m0 x5 h8 ya ff4 fs0 fc0 sc0 ls1 ws0"> </div><div class="t m0 x6 h7 yb ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span>C<span class="ff8">&#417;</span><span class="ls14"> b</span><span class="ff8">&#7843;</span><span class="ls7 ws11">n v</span><span class="ff8">&#7873;</span><span class="ls1d ws1"> thi</span><span class="ff8">&#7871;</span><span class="ls0 ws1f">t k</span><span class="ff8">&#7871;</span><span class="ls14"> s</span><span class="ff8">&#7889;</span><span class="ls14">, </span></div><div class="t m0 x6 h7 yc ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span>C<span class="ff8">&#417;</span><span class="ls14"> b</span><span class="ff8">&#7843;</span><span class="ls7 ws11">n v</span><span class="ff8">&#7873;</span><span class="ls24 ws23"> ng&#244;n ng</span><span class="ff8">&#7919;</span><span class="ls25 ws24"> m&#244; t</span><span class="ff8">&#7843;</span><span class="ls26 ws25"> ph</span><span class="ff8">&#7847;</span><span class="ls7 ws11">n c</span><span class="ff8">&#7913;</span><span class="ls27 ws26">ng VHDL, </span></div><div class="t m0 x6 h7 yd ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span>N<span class="ff8">&#7855;</span><span class="ls9 ws27">m r&#245; c&#225;ch s</span><span class="ff8">&#7917;</span><span class="ls14"> d</span><span class="ff8">&#7909;</span><span class="ls5 ws28">ng kit DE1. </span></div><div class="t m0 x3 h6 ye ff4 fs0 fc0 sc0 ls7 ws0">3.<span class="ff6 ls1"> <span class="_ _3"> </span></span><span class="ls20 ws20">C&#225;c ki</span><span class="ff5 ls1">&#7871;</span><span class="ls17 ws12">n th</span><span class="ff5 ls1">&#7913;</span><span class="ls20 ws20">c thu </span><span class="ff5 ls3">&#273;&#432;&#7907;</span><span class="ls1">c</span></div><div class="t m0 x7 h8 yf ff4 fs0 fc0 sc0 ls1 ws0"> </div><div class="t m0 x6 h7 y10 ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls28">Bi</span><span class="ff8">&#7871;</span><span class="ls20 ws20">t c&#225;ch t</span><span class="ff8">&#7841;</span><span class="ls7 ws29">o m</span><span class="ff8">&#7897;</span><span class="ls0 ws1f">t d</span><span class="ff8">&#7921;</span><span class="ls1d ws1"> &#225;n tr&#234;n ph</span><span class="ff8">&#7847;</span><span class="ls7 ws11">n m</span><span class="ff8">&#7873;</span><span class="ls29 ws2a">m Quartus <span class="_ _4"></span>II. </span></div><div class="t m0 x6 h7 y11 ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls28">Bi</span><span class="ff8">&#7871;</span><span class="ls20 ws20">t c&#225;ch t</span><span class="ff8">&#7893;</span><span class="ls7 ws11">ng h</span><span class="ff8">&#7907;</span><span class="ls7 ws11">p m</span><span class="ff8">&#7841;</span><span class="ls0 ws1f">ch logic t</span><span class="ff8">&#7915;</span><span class="ls6 ws2b"> m&#227; VHDL d&#249;ng tr&#236;nh t</span><span class="ff8">&#7893;</span><span class="ls7 ws11">ng h</span><span class="ff8">&#7907;</span><span class="ls1d ws1">p t<span class="_ _4"></span>&#237;ch h<span class="ff8 ls1 ws0">&#7907;</span><span class="ls7 ws11">p s<span class="ff8 ls1 ws0">&#7861;</span>n c<span class="ff8 ls1 ws0">&#7911;</span><span class="ls2a ws2c">a Quartus II. </span></span></span></div><div class="t m0 x6 h7 y12 ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls28">Bi</span><span class="ff8">&#7871;</span><span class="ls15 wsf">t c&#225;ch th</span><span class="ff8">&#7921;</span><span class="ls17 ws12">c hi</span><span class="ff8">&#7879;</span><span class="ls2b ws3">n m&#244; ph</span><span class="ff8">&#7887;</span><span class="ls5 ws28">ng cho m</span><span class="ff8">&#7841;</span><span class="ls6 ws2b">ch logic. </span></div><div class="t m0 x6 h7 y13 ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls28">Bi</span><span class="ff8">&#7871;</span><span class="ls29 ws2d">t c&#225;ch g&#225;n ch&#226;n cho FPGA </span><span class="ff8 ls7">&#273;&#7875;</span> <span class="ff8 ls7">&#273;&#432;</span><span class="ls20 ws20">a c&#225;c t&#237;n hi</span><span class="ff8">&#7879;</span><span class="ls8 ws2e">u v&#224;o ra m</span><span class="ff8">&#7841;</span><span class="ls0 ws1f">ch logic n</span><span class="ff8">&#7889;</span><span class="ls0 ws1f">i v</span><span class="ff8">&#7899;</span><span class="ls2c ws2f">i c&#225;c ch&#226;n tr&#234;n FPGA. </span></div><div class="t m0 x6 h7 y14 ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls28">Bi</span><span class="ff8">&#7871;</span><span class="ls20 ws20">t c&#225;ch n</span><span class="ff8">&#7841;</span><span class="ls2d ws30">p v&#224; c<span class="_ _4"></span><span class="ff8 ls1 ws0">&#7845;<span class="ff7 ls1d ws1">u h&#236;nh cho FPGA </span></span></span></div><div class="t m0 x3 h6 y15 ff4 fs0 fc0 sc0 ls7 ws0">4.<span class="ff6 ls1"> <span class="_ _3"> </span></span><span class="ls1b ws15">C&#225;c b</span><span class="ff5 ls2e">&#432;&#7899;</span><span class="ls21 ws21">c th</span><span class="ff5 ls1">&#7921;<span class="ff4 ws10">c hi</span>&#7879;</span><span class="ls2 ws31">n m</span><span class="ff5 ls1">&#7897;</span><span class="ls15 ws32">t thi</span><span class="ff5 ls1">&#7871;</span><span class="ls20 ws20">t k</span><span class="ff5 ls1">&#7871;</span></div><div class="t m0 x8 h8 y16 ff4 fs0 fc0 sc0 ls1 ws0"> </div><div class="t m0 x3 h7 y17 ff7 fs0 fc0 sc0 ls1a ws33">C&#225;c b<span class="ff8 ws0">&#432;&#7899;</span><span class="ls1b ws15">c th<span class="ff8 ls1 ws0">&#7875;</span><span class="ls26 ws25"> hi<span class="ff8 ls1 ws0">&#7879;</span><span class="ls2f ws4">n quy tr&#236;nh thi<span class="ff8 ls1 ws0">&#7871;</span><span class="ls0 ws1f">t k<span class="ff8 ls1 ws0">&#7871;<span class="ff7 ls14"> s</span>&#7889;<span class="ff7 ws10"> tr&#234;n c&#225;c IC c&#243; th</span>&#7875;<span class="ff7 ls14"> l</span>&#7853;<span class="ff7 ls14">p tr&#236;nh (FPGA/CPLD) nh</span>&#432;</span><span class="ls9 ws27"> sau: </span></span></span></span></span></div><div class="t m0 x9 h9 y18 ff7 fs0 fc0 sc0 ls1 ws0"> </div><div class="t m0 xa ha y19 ff7 fs3 fc0 sc0 ls30 ws34">H&#236;nh 1. Qu<span class="_ _2"></span>y tr&#236;nh thi<span class="_ _2"></span><span class="ff8 ls1 ws0">&#7871;</span><span class="ls31 ws35">t k<span class="ff8 ls1 ws0">&#7871;</span> CAD th&#244;ng d<span class="ff8 ls1 ws0">&#7909;<span class="ff7 ls32">ng </span></span></span></div><div class="t m0 x6 h7 y1a ff7 fs0 fc0 sc0 ls1 ws0">-<span class="ff1"> <span class="_ _5"> </span></span><span class="ls4">Nh</span><span class="ff8">&#7853;</span><span class="ls16 ws36">p thi</span><span class="ff8">&#7871;</span><span class="ls0 ws37">t k</span><span class="ff8">&#7871;</span><span class="ls0 ws37">: M</span><span class="ff8">&#7841;</span><span class="ls14 ws38">ch logic mong mu</span><span class="ff8">&#7889;</span><span class="ls7">n <span class="_ _6"> </span><span class="ff8 ls0">&#273;&#432;&#7907;</span><span class="ls23 ws39">c m&#244; t</span></span><span class="ff8">&#7843;</span><span class="ls33"> b<span class="_ _7"></span><span class="ff8 ls1">&#7857;<span class="ff7 ls7 ws3a">ng ng&#244;n ng</span>&#7919;<span class="ff7 ls25 ws3b"> m&#244; t</span>&#7843;<span class="ff7 ls7 ws3a"> ph</span>&#7847;<span class="ff7 ls7 ws3a">n c</span>&#7913;<span class="ff7 ls7 ws3a">ng nh</span>&#432;<span class="ff7"> </span></span></span></div><div class="t m0 xb h7 y1b ff7 fs0 fc0 sc0 ls20 ws20">VHDL/Verilog ho<span class="ff8 ls1 ws0">&#7863;</span><span class="ls23 ws22">c b<span class="ff8 ls1 ws0">&#7857;</span><span class="ls7 ws30">ng s<span class="ff8 ls1 ws0">&#417;<span class="ff7"> </span><span class="ls7">&#273;&#7891;<span class="ff7 ls14"> m</span></span>&#7841;<span class="ff7 ls3">ch. </span></span></span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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