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eepromVerilog24c32code并带有文档资料
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/622b3c9eff7f9c46a613a896/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3c9eff7f9c46a613a896/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"><span class="fc1 sc0">1</span></div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">Features</div><div class="t m0 x2 h2 y3 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls2 ws1">Low<span class="_ _1"></span>-vo<span class="_ _1"></span>ltage and Stan<span class="_ _1"></span>dar<span class="_ _1"></span>d-v<span class="_ _1"></span>oltage Opera<span class="_ _1"></span>tion</span></div><div class="t m0 x3 h4 y4 ff1 fs2 fc0 sc0 ls3 ws1">&#8211;<span class="_ _2"> </span>5.0 (V</div><div class="t m0 x4 h5 y5 ff1 fs3 fc0 sc0 ls4 ws0">CC</div><div class="t m0 x5 h4 y4 ff1 fs2 fc0 sc0 ls5 ws2"> = 4.5V to 5.<span class="_ _1"></span>5V)</div><div class="t m0 x3 h4 y6 ff1 fs2 fc0 sc0 ls3 ws3">&#8211;<span class="_ _2"> </span>2.7 (V</div><div class="t m0 x4 h5 y7 ff1 fs3 fc0 sc0 ls4 ws0">CC</div><div class="t m0 x5 h4 y6 ff1 fs2 fc0 sc0 ls5 ws2"> = 2.7V to 5.<span class="_ _1"></span>5V)</div><div class="t m0 x3 h4 y8 ff1 fs2 fc0 sc0 ls3 ws3">&#8211;<span class="_ _2"> </span>2.5 (V</div><div class="t m0 x4 h5 y9 ff1 fs3 fc0 sc0 ls4 ws0">CC</div><div class="t m0 x5 h4 y8 ff1 fs2 fc0 sc0 ls5 ws2"> = 2.5V to 5.<span class="_ _1"></span>5V)</div><div class="t m0 x3 h4 ya ff1 fs2 fc0 sc0 ls3 ws3">&#8211;<span class="_ _2"> </span>1.8 (V</div><div class="t m0 x4 h5 yb ff1 fs3 fc0 sc0 ls4 ws0">CC</div><div class="t m0 x5 h4 ya ff1 fs2 fc0 sc0 ls5 ws2"> = 1.8V to 5.<span class="_ _1"></span>5V)</div><div class="t m0 x2 h2 yc ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls6 ws4">Interna<span class="_ _1"></span>lly <span class="_ _1"></span>Org<span class="_ _1"></span>anized 128 x<span class="_ _1"></span> 8 (1K)<span class="_ _1"></span>, 256 x 8 (2<span class="_ _1"></span>K), 512 x<span class="_ _1"></span> 8 (4K),</span></div><div class="t m0 x6 h4 yd ff1 fs2 fc0 sc0 ls6 ws4">1024 x 8<span class="_ _1"></span> (8K) <span class="_ _1"></span>or 2048 x 8 <span class="_ _1"></span>(16K)</div><div class="t m0 x2 h2 ye ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls7 ws5">2-wire Serial Interface</span></div><div class="t m0 x2 h2 yf ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls2 ws1">Schmitt <span class="_ _1"></span>T<span class="_ _3"></span>rigger<span class="_ _3"></span>, Filtered Inputs <span class="_ _1"></span>for No<span class="_ _1"></span>ise Suppressi<span class="_ _1"></span>on</span></div><div class="t m0 x2 h2 y10 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls8 ws6">Bi-direc<span class="_ _1"></span>tional Data<span class="_ _1"></span> T<span class="_ _3"></span>ransfer<span class="_ _1"></span> Prot<span class="_ _1"></span>ocol</span></div><div class="t m0 x2 h2 y11 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls9 ws7">100 kH<span class="_ _1"></span>z (1.8V<span class="_ _4"></span>, 2.5V<span class="_ _4"></span>, 2.7V) and 400 <span class="_ _1"></span>kHz (5V) C<span class="_ _1"></span>ompatibili<span class="_ _1"></span>ty</span></div><div class="t m0 x2 h2 y12 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 lsa ws8">Write Pr<span class="_ _1"></span>otect Pin <span class="_ _1"></span>for Har<span class="_ _1"></span>dware<span class="_ _1"></span> Data Pr<span class="_ _1"></span>otection</span></div><div class="t m0 x2 h2 y13 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls2 ws1">8-b<span class="_ _1"></span>yte P<span class="_ _1"></span>age (1K, <span class="_ _1"></span>2K), 16-b<span class="_ _1"></span>yte P<span class="_ _1"></span>age (4<span class="_ _1"></span>K, 8K, 16K) W<span class="_ _1"></span>rite Modes</span></div><div class="t m0 x2 h2 y14 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 lsb ws9">P<span class="_ _1"></span>artial P<span class="_ _1"></span>age Writes are<span class="_ _1"></span> Allowe<span class="_ _1"></span>d</span></div><div class="t m0 x2 h2 y15 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 lsc wsa">Self-timed W<span class="_ _1"></span>rite Cyc<span class="_ _1"></span>le (10 m<span class="_ _1"></span>s max)</span></div><div class="t m0 x2 h2 y16 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 lsd">High<span class="_ _5"></span>-re<span class="_ _5"></span>lia<span class="_ _5"></span>bili<span class="_ _5"></span>ty</span></div><div class="t m0 x3 h4 y17 ff1 fs2 fc0 sc0 lse ws0">&#8211;<span class="_ _2"> </span>Enduran<span class="_ _1"></span>ce: 1 Millio<span class="_ _1"></span>n Write Cyc<span class="_ _1"></span>les</div><div class="t m0 x3 h4 y18 ff1 fs2 fc0 sc0 ls9 ws7">&#8211;<span class="_ _2"> </span>Data Re<span class="_ _1"></span>tention: 10<span class="_ _1"></span>0 Y<span class="_ _3"></span>ear<span class="_ _1"></span>s</div><div class="t m0 x2 h2 y19 ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 lsf wsb">A<span class="_ _1"></span>utomo<span class="_ _1"></span>tive Grade and Extended T<span class="_ _3"></span>emperature D<span class="_ _1"></span>evices<span class="_ _1"></span> A<span class="_ _1"></span>v<span class="_ _1"></span>ailable</span></div><div class="t m0 x2 h2 y1a ff2 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _0"> </span><span class="ff1 fs2 ls10 wsc">8-lead JEDEC <span class="_ _1"></span>SOIC, 8-pin PDIP a<span class="_ _1"></span>nd 8-lead TSSOP P<span class="_ _3"></span>ackages</span></div><div class="t m0 x2 h3 y1b ff1 fs1 fc0 sc0 ls11 ws0">Description</div><div class="t m0 x2 h2 y1c ff2 fs0 fc0 sc0 ls12 wsd">The AT24<span class="_ _5"></span>C01A/02/04<span class="_ _5"></span>/08/16 <span class="_ _5"></span>provides <span class="_ _5"></span>1024/2048/4<span class="_ _5"></span>096/8192/1<span class="_ _5"></span>6384 bits<span class="_ _5"></span> of ser<span class="_ _5"></span>ial elec-</div><div class="t m0 x2 h2 y1d ff2 fs0 fc0 sc0 ls13 wse">trically eras<span class="_ _5"></span>able and programmable <span class="_ _5"></span>read-only memory (<span class="_ _5"></span>EEPROM) organi<span class="_ _5"></span>zed as</div><div class="t m0 x2 h2 y1e ff2 fs0 fc0 sc0 ls14 wsf">128/256/51<span class="_ _5"></span>2/1024/2<span class="_ _5"></span>048 words of 8 b<span class="_ _5"></span>its each.<span class="_ _5"></span> The devi<span class="_ _5"></span>ce is opt<span class="_ _5"></span>imized fo<span class="_ _5"></span>r use in many</div><div class="t m0 x2 h2 y1f ff2 fs0 fc0 sc0 ls15 ws10">indust<span class="_ _1"></span>rial a<span class="_ _1"></span>nd co<span class="_ _1"></span>mmerci<span class="_ _1"></span>al appli<span class="_ _1"></span>catio<span class="_ _1"></span>ns wh<span class="_ _1"></span>ere l<span class="_ _1"></span>ow-powe<span class="_ _1"></span>r and<span class="_ _1"></span> low-<span class="_ _1"></span>voltage<span class="_ _1"></span> oper<span class="_ _1"></span>ation</div><div class="t m0 x2 h2 y20 ff2 fs0 fc0 sc0 ls16 ws11">are essen<span class="_ _5"></span>tial. T<span class="_ _5"></span>he AT24C<span class="_ _5"></span>01A/02/<span class="_ _5"></span>04/08/16<span class="_ _5"></span> is availab<span class="_ _5"></span>le in spa<span class="_ _5"></span>ce-sav<span class="_ _5"></span>ing 8-pin P<span class="_ _5"></span>DIP,</div><div class="t m0 x2 h2 y21 ff2 fs0 fc0 sc0 ls17 ws12">(AT24C01A/02/04/08/16)<span class="_ _5"></span>, 8-lead TSSOP (<span class="_ _5"></span>AT24C01A/02/04/08<span class="_ _5"></span>/16) and 8-lead</div><div class="t m0 x2 h2 y22 ff2 fs0 fc0 sc0 ls18 ws13">JEDEC SO<span class="_ _5"></span>IC (AT24<span class="_ _5"></span>C01A/<span class="_ _5"></span>02/04/<span class="_ _5"></span>08/16) pa<span class="_ _5"></span>ckages and<span class="_ _5"></span> is access<span class="_ _5"></span>ed via a 2-wi<span class="_ _5"></span>re serial</div><div class="t m0 x2 h2 y23 ff2 fs0 fc0 sc0 ls18 ws14">interfac<span class="_ _5"></span>e. In additio<span class="_ _5"></span>n, the entire<span class="_ _5"></span> family is ava<span class="_ _5"></span>ilable in<span class="_ _5"></span> 5.0V (4.5V<span class="_ _5"></span> to 5.5V), 2.7V (2<span class="_ _5"></span>.7V to</div><div class="t m0 x2 h2 y24 ff2 fs0 fc0 sc0 ls19 ws15">5.5V), 2.<span class="_ _5"></span>5V (2.5V<span class="_ _5"></span> to 5.5V) and<span class="_ _5"></span> 1.8V (1.8<span class="_ _5"></span>V to 5.5V)<span class="_ _5"></span> version<span class="_ _5"></span>s.</div><div class="t m0 x7 h6 y25 ff1 fs4 fc0 sc0 ls7 ws0">2-wire</div><div class="t m0 x7 h6 y26 ff1 fs4 fc0 sc0 ls7 ws16">Serial EEPROM</div><div class="t m0 x7 h7 y27 ff1 fs5 fc0 sc0 ls1a ws17">1K (1<span class="_ _1"></span>28 x 8<span class="_ _1"></span>)</div><div class="t m0 x7 h7 y28 ff1 fs5 fc0 sc0 ls1a ws17">2K (2<span class="_ _1"></span>56 x 8<span class="_ _1"></span>)</div><div class="t m0 x7 h7 y29 ff1 fs5 fc0 sc0 ls1a ws17">4K (5<span class="_ _1"></span>12 x 8<span class="_ _1"></span>)</div><div class="t m0 x7 h7 y2a ff1 fs5 fc0 sc0 ls1b ws18">8K (1<span class="_ _1"></span>024 x<span class="_ _1"></span> 8)</div><div class="t m0 x7 h7 y2b ff1 fs5 fc0 sc0 ls1c ws19">16K (<span class="_ _1"></span>2048 x 8<span class="_ _1"></span>)</div><div class="t m0 x7 h6 y2c ff1 fs4 fc0 sc0 ls1d ws0">AT24C01A</div><div class="t m0 x7 h6 y2d ff1 fs4 fc0 sc0 ls1e ws0">AT24C02</div><div class="t m0 x7 h6 y2e ff1 fs4 fc0 sc0 ls1e ws0">AT24C04</div><div class="t m0 x7 h6 y2f ff1 fs4 fc0 sc0 ls1e ws0">AT24C08</div><div class="t m0 x7 h6 y30 ff1 fs4 fc0 sc0 ls1e ws0">AT24C16</div><div class="t m0 x8 h8 y31 ff2 fs6 fc0 sc0 ls1f ws1a">Rev<span class="_ _1"></span>. 0180<span class="_ _1"></span>E&#8211;09<span class="_ _1"></span>/00</div><div class="t m0 x2 h3 y32 ff1 fs1 fc0 sc0 ls20 ws1b">Pin Configurations</div><div class="t m0 x9 h4 y33 ff1 fs2 fc0 sc0 ls3 ws3">Pin Name<span class="_ _6"> </span>Function</div><div class="t m0 x9 h4 y34 ff2 fs2 fc0 sc0 lsb ws9">A0 - A2<span class="_ _7"> </span>Address Inputs</div><div class="t m0 x9 h4 y35 ff2 fs2 fc0 sc0 ls6 ws4">SD<span class="_ _1"></span>A<span class="_ _8"> </span>Serial Data</div><div class="t m0 x9 h4 y36 ff2 fs2 fc0 sc0 ls21 ws1c">SCL<span class="_ _9"> </span>Serial Cloc<span class="_ _1"></span>k <span class="_ _1"></span>Input </div><div class="t m0 x9 h4 y37 ff2 fs2 fc0 sc0 ls22 ws1d">WP<span class="_ _a"> </span>Write Protect</div><div class="t m0 x9 h4 y38 ff2 fs2 fc0 sc0 ls23 ws1e">NC<span class="_ _b"> </span>No Connect</div><div class="t m0 xa h4 y39 ff2 fs2 fc0 sc0 ls24 ws1f">8-le<span class="_ _5"></span>ad SO<span class="_ _5"></span>IC</div><div class="t m0 xb h9 y3a ff3 fs7 fc0 sc0 ls0 ws0">1</div><div class="t m0 xb h9 y3b ff3 fs7 fc0 sc0 ls0 ws0">2</div><div class="t m0 xb h9 y3c ff3 fs7 fc0 sc0 ls0 ws0">3</div><div class="t m0 xb h9 y3d ff3 fs7 fc0 sc0 ls0 ws0">4</div><div class="t m0 xc h9 y3e ff3 fs7 fc0 sc0 ls0 ws0">8</div><div class="t m0 xc h9 y3f ff3 fs7 fc0 sc0 ls0 ws0">7</div><div class="t m0 xc h9 y40 ff3 fs7 fc0 sc0 ls0 ws0">6</div><div class="t m0 xc h9 y41 ff3 fs7 fc0 sc0 ls0 ws0">5</div><div class="t m0 xd h9 y3a ff3 fs7 fc0 sc0 ls0 ws0">A0</div><div class="t m0 xd h9 y3b ff3 fs7 fc0 sc0 ls0 ws0">A1</div><div class="t m0 xd h9 y3c ff3 fs7 fc0 sc0 ls0 ws0">A2</div><div class="t m0 xe h9 y3d ff3 fs7 fc0 sc0 ls0 ws0">GND</div><div class="t m0 xf h9 y3a ff3 fs7 fc0 sc0 ls0 ws0">VCC</div><div class="t m0 xf h9 y3b ff3 fs7 fc0 sc0 ls25 ws0">WP</div><div class="t m0 xf h9 y3c ff3 fs7 fc0 sc0 ls0 ws0">SCL</div><div class="t m0 xf h9 y3d ff3 fs7 fc0 sc0 ls0 ws0">SDA</div><div class="t m0 x10 h4 y39 ff3 fs2 fc0 sc0 ls26 ws20">8-pin PD<span class="_ _1"></span>IP</div><div class="t m0 x4 h9 y42 ff3 fs7 fc0 sc0 ls0 ws0">1</div><div class="t m0 x4 h9 y43 ff3 fs7 fc0 sc0 ls0 ws0">2</div><div class="t m0 x4 h9 y44 ff3 fs7 fc0 sc0 ls0 ws0">3</div><div class="t m0 x4 h9 y45 ff3 fs7 fc0 sc0 ls0 ws0">4</div><div class="t m0 x11 h9 y46 ff3 fs7 fc0 sc0 ls0 ws0">8</div><div class="t m0 x11 h9 y47 ff3 fs7 fc0 sc0 ls0 ws0">7</div><div class="t m0 x11 h9 y48 ff3 fs7 fc0 sc0 ls0 ws0">6</div><div class="t m0 x11 h9 y49 ff3 fs7 fc0 sc0 ls0 ws0">5</div><div class="t m0 x12 h9 y42 ff3 fs7 fc0 sc0 ls0 ws0">A0</div><div class="t m0 x12 h9 y43 ff3 fs7 fc0 sc0 ls0 ws0">A1</div><div class="t m0 x12 h9 y44 ff3 fs7 fc0 sc0 ls0 ws0">A2</div><div class="t m0 x13 h9 y45 ff3 fs7 fc0 sc0 ls0 ws0">GND</div><div class="t m0 x14 h9 y46 ff3 fs7 fc0 sc0 ls0 ws0">VCC</div><div class="t m0 x14 h9 y47 ff3 fs7 fc0 sc0 ls25 ws0">WP</div><div class="t m0 x14 h9 y48 ff3 fs7 fc0 sc0 ls0 ws0">SCL</div><div class="t m0 x14 h9 y49 ff3 fs7 fc0 sc0 ls0 ws0">SDA</div><div class="t m0 x15 h4 y4a ff3 fs2 fc0 sc0 ls26 ws21">8-lead TSSOP</div><div class="t m0 xa h9 y4b ff3 fs7 fc0 sc0 ls0 ws0">1</div><div class="t m0 xa h9 y4c ff3 fs7 fc0 sc0 ls0 ws0">2</div><div class="t m0 xa h9 y4d ff3 fs7 fc0 sc0 ls0 ws0">3</div><div class="t m0 xa h9 y4e ff3 fs7 fc0 sc0 ls0 ws0">4</div><div class="t m0 x16 h9 y4f ff3 fs7 fc0 sc0 ls0 ws0">8</div><div class="t m0 x16 h9 y50 ff3 fs7 fc0 sc0 ls0 ws0">7</div><div class="t m0 x16 h9 y51 ff3 fs7 fc0 sc0 ls0 ws0">6</div><div class="t m0 x16 h9 y52 ff3 fs7 fc0 sc0 ls0 ws0">5</div><div class="t m0 x17 h9 y53 ff3 fs7 fc0 sc0 ls0 ws0">A0</div><div class="t m0 x17 h9 y54 ff3 fs7 fc0 sc0 ls0 ws0">A1</div><div class="t m0 x17 h9 y55 ff3 fs7 fc0 sc0 ls0 ws0">A2</div><div class="t m0 x18 h9 y56 ff3 fs7 fc0 sc0 ls0 ws0">GND</div><div class="t m0 x19 h9 y4f ff3 fs7 fc0 sc0 ls0 ws0">VCC</div><div class="t m0 x19 h9 y50 ff3 fs7 fc0 sc0 ls25 ws0">WP</div><div class="t m0 x19 h9 y51 ff3 fs7 fc0 sc0 ls0 ws0">SCL</div><div class="t m0 x19 h9 y52 ff3 fs7 fc0 sc0 ls0 ws0">SDA</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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