FSM-Based-Using-Verilog-HDL.rar_verilog_VHDL/FPGA/Verilog_嵌入式/单片机/硬件编程下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">8</div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">Describing Combinational</div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls0 ws0">and Sequential Logic using</div><div class="t m0 x1 h3 y4 ff1 fs1 fc0 sc0 ls0 ws0">Verilog HDL</div><div class="t m0 x1 h4 y5 ff2 fs2 fc0 sc0 ls0 ws0">8.1 THE DATA-FLOW STYLE OF DESCRIPTION:</div><div class="t m0 x1 h4 y6 ff2 fs2 fc0 sc0 ls0 ws0">REVIEW OF THE CONTINUOUS ASSIGNMENT</div><div class="t m0 x1 h5 y7 ff3 fs3 fc0 sc0 ls0 ws0">We have already come across numerous examples in the previous chapters of Verilog designs</div><div class="t m0 x1 h5 y8 ff3 fs3 fc0 sc0 ls0 ws0">written in the so-called data-ﬂow style. This style of description makes use of the para llel</div><div class="t m0 x1 h5 y9 ff3 fs3 fc0 sc0 ls0 ws0">statement known as a continuous assignment. Predominantly used to describe combinational</div><div class="t m0 x1 h5 ya ff3 fs3 fc0 sc0 ls0 ws0">logic, the ﬂow of execution of continuous assignment statements is dictated by events on signals</div><div class="t m0 x1 h5 yb ff3 fs3 fc0 sc0 ls0 ws0">(usually wires) appearing within the expressions on the left- and right-hand sides of the</div><div class="t m0 x1 h5 yc ff3 fs3 fc0 sc0 ls0 ws0">continuous assignm ents. Such statements are identiﬁed by the keyword assign. The keyword</div><div class="t m0 x1 h5 yd ff3 fs3 fc0 sc0 ls0 ws0">is followed by one or more assignments terminated by a semicolon.</div><div class="t m0 x2 h5 ye ff3 fs3 fc0 sc0 ls0 ws0">All of the following examples describe combinational logic, this being the most common use</div><div class="t m0 x1 h5 yf ff3 fs3 fc0 sc0 ls0 ws0">of the continuous assignment statement:</div><div class="t m0 x2 h6 y10 ff6 fs3 fc0 sc0 ls0 ws0">//some continuous assignment statements</div><div class="t m0 x3 h7 y11 ff5 fs3 fc0 sc0 ls0 ws0">assign A ¼ q[0], B ¼ q[1], C ¼ q[2];</div><div class="t m0 x3 h7 y12 ff5 fs3 fc0 sc0 ls0 ws0">assign out ¼ (s1 & s0 & i0) j</div><div class="t m0 x4 h7 y13 ff7 fs3 fc0 sc0 ls0 ws0">(s1 & s0 & i1) j</div><div class="t m0 x4 h7 y14 ff7 fs3 fc0 sc0 ls0 ws0">(s1 & s0 & i2) j</div><div class="t m0 x4 h6 y15 ff7 fs3 fc0 sc0 ls0 ws0">(s1 & s0 & i3);</div><div class="t m0 x3 h7 y16 ff5 fs3 fc0 sc0 ls0 ws0">assign #15 {c_out, sum} ¼ a þ b þ c_in;</div><div class="t m0 x2 h5 y17 ff3 fs3 fc0 sc0 ls0 ws0">The continuous assignment statement forms a static binding between the wire being assigned</div><div class="t m0 x1 h7 y18 ff3 fs3 fc0 sc0 ls4 ws0">on the left-hand side of the ¼ operator and the expression on the right-hand side of the assignment</div><div class="t m0 x1 h5 y19 ff3 fs3 fc0 sc0 ls0 ws0">operator. This means that the assignment is continuously active and ready to respond to any</div><div class="t m0 x1 h8 y1a ff9 fs4 fc0 sc0 ls0 ws0">FSM-based Digital Design using Verilog HDL Peter Minns and Ian Elliott</div><div class="t m0 x1 h9 y1b ffb fs4 fc0 sc0 ls0 ws0">#</div><div class="t m0 x5 h8 y1c ffb fs4 fc0 sc0 ls0 ws2"> 2008 John Wiley & Sons, Ltd. ISBN: 978-0-470-06070-4</div></div><div class="pi" data-data='{"ctm":[1.961965,0.000000,0.000000,1.961965,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/bg2.jpg"><div class="t m0 x6 h5 y1d ff3 fs3 fc0 sc0 ls0 ws0">changes to variables appearing in the right-hand side expression (the inputs). Such changes result</div><div class="t m0 x6 h5 y1e ff3 fs3 fc0 sc0 ls7 ws0">in the ev aluation of the expression and updating of the target wire (output). In this manner, a</div><div class="t m0 x6 h5 y1f ff3 fs3 fc0 sc0 ls0 ws0">continuous assignment is almost exclusively used to describe combinatorial logic.</div><div class="t m0 x7 h5 y20 ff3 fs3 fc0 sc0 ls0 ws0">As mentioned previously, a Verilog module may contain any number of continuous assign-</div><div class="t m0 x6 h5 y21 ff3 fs3 fc0 sc0 ls0 ws0">ment statements; they can be inserted anywhere between the module header and internal wire/</div><div class="t m0 x6 h5 y22 ff5 fs3 fc0 sc0 ls0 ws0">reg declarations and the endmodule keyword.</div><div class="t m0 x7 h5 y23 ff3 fs3 fc0 sc0 ls0 ws0">The expression appearing on the right-hand side of the assignment operator may contain</div><div class="t m0 x6 h5 y24 ff3 fs3 fc0 sc0 ls8 ws0">both reg-andwire-type v ariables and make use of any of the Verilog operators mentioned in</div><div class="t m0 x6 h5 y25 ff3 fs3 fc0 sc0 lsc ws0">Chapter 7.</div><div class="t m0 x7 h5 y26 ff3 fs3 fc0 sc0 lsd ws0">The so-called target of the assignment (left-hand side) must be a wire, since it is continuously</div><div class="t m0 x6 h5 y27 ff4 fs3 fc0 sc0 ls10 ws0">driven. Both single-bit and multi-bit wires may be the targets of continuous assignment statements.</div><div class="t m0 x7 h5 y28 ff3 fs3 fc0 sc0 ls0 ws0">It is possible, although not common practice, to use the continuous assignment statement to</div><div class="t m0 x6 h5 y29 ff3 fs3 fc0 sc0 ls0 ws0">describe sequential logic, in the form of a level-sensitive latch.</div><div class="t m0 x7 h5 y2a ff3 fs3 fc0 sc0 ls0 ws0">The conditional operator (?:) is used on the right-hand side of the assignment on line 2 of the</div><div class="t m0 x6 h5 y2b ff3 fs3 fc0 sc0 ls0 ws0">listing shown in Figure 8.1. When en is true (logic 1) the output q is assigned the value of the</div><div class="t m0 x6 h5 y2c ff3 fs3 fc0 sc0 ls0 ws0">input data continuously. When en goes to logic 0, the output q is assigned itself, i.e. feedback</div><div class="t m0 x6 h5 y2d ff3 fs3 fc0 sc0 ls0 ws0">maintains the value of q, as shown in the logic diagram below the Verilog listing.</div><div class="t m0 x7 h5 y2e ff3 fs3 fc0 sc0 ls0 ws0">It should be noted that the use of a continuous assignment to crea te a level-sensitive latch, as</div><div class="t m0 x6 h5 y2f ff3 fs3 fc0 sc0 ls0 ws0">shown in Figure 8.1, is relatively uncommon. Most logic synthesis software tools will issue a</div><div class="t m0 x6 h5 y30 ff3 fs3 fc0 sc0 ls0 ws0">warning message on encountering such a construct.</div><div class="t m0 x6 h4 y31 ff2 fs2 fc0 sc0 ls14 ws0">8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION:</div><div class="t m0 x6 h4 y32 ff2 fs2 fc0 sc0 ls0 ws0">THE SEQUENTIAL BLOCK</div><div class="t m0 x6 h5 y33 ff3 fs3 fc0 sc0 ls0 ws0">The Verilog HDL sequential block deﬁnes a region within the hardware description conta-</div><div class="t m0 x6 h5 y34 ff3 fs3 fc0 sc0 ls0 ws0">ining sequential statements; these statements execute in the order they are wr itten, in just the</div><div class="t m0 x8 ha y35 ffc fs5 fc0 sc0 ls0 ws0">1 module latch (output q, input data, en); </div><div class="t m0 x8 ha y36 ffc fs5 fc0 sc0 ls0 ws0">2 assign q = en ? data : q; </div><div class="t m0 x8 ha y37 ffc fs5 fc0 sc0 ls0 ws0">3 endmodule</div><div class="t m0 x9 hb y38 ffe fs6 fc0 sc0 ls1a ws0">MUX</div><div class="t m0 xa hc y39 fff fs7 fc0 sc0 ls0 ws0">1</div><div class="t m0 xa hc y3a fff fs7 fc0 sc0 ls0 ws0">0</div><div class="t m0 xb hd y3b fff fs6 fc0 sc0 ls0 ws0">q</div><div class="t m0 xc hd y3c fff fs6 fc0 sc0 ls1b ws0">en</div><div class="t m0 xd hd y3d fff fs6 fc0 sc0 ls1b ws0">data</div><div class="t m0 xe he y3e ff10 fs8 fc0 sc0 ls0 ws0">Figure 8.1 Describing a level-sensitive latch using a continuous assignment.</div><div class="t m0 x6 hf y3f ff1 fs8 fc0 sc0 ls0 ws0">198 Describing Combinational and Sequential Logic using Verilog HDL</div></div><div class="pi" data-data='{"ctm":[1.961965,0.000000,0.000000,1.961965,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/bg3.jpg"><div class="t m0 x1 h5 y40 ff3 fs3 fc0 sc0 ls0 ws0">same way as a conventional programming language. In this manner, the sequential block</div><div class="t m0 x1 h5 y41 ff3 fs3 fc0 sc0 ls0 ws0">provides a mechanism for creating hardware descriptions that are behavioural or algorithmic.</div><div class="t m0 x1 h5 y42 ff3 fs3 fc0 sc0 ls0 ws0">Such a style lends itself ideally to the description of synchronous sequential logic, such as</div><div class="t m0 x1 h5 y43 ff3 fs3 fc0 sc0 ls0 ws0">counters and FSMs; however, sequential blocks can also be used to describe combinational</div><div class="t m0 x1 h5 y44 ff3 fs3 fc0 sc0 ls0 ws0">functions.</div><div class="t m0 x2 h5 y45 ff3 fs3 fc0 sc0 ls0 ws0">A discussion of some of the more commonly used Verilog sequential statements will reveal</div><div class="t m0 x1 h5 y46 ff3 fs3 fc0 sc0 ls0 ws0">their similarity to the statements used in the C language. In addition to the two types of sequential</div><div class="t m0 x1 h5 y47 ff3 fs3 fc0 sc0 ls0 ws0">block described below, Verilog HDL makes use of sequential execution in the so-called task</div><div class="t m0 x1 h5 y48 ff3 fs3 fc0 sc0 ls0 ws0">and function elements of the language. These elements are beyond the scope of this book; the</div><div class="t m0 x1 h5 y49 ff3 fs3 fc0 sc0 ls0 ws0">interested reader is referred to Reference [1].</div><div class="t m0 x2 h5 y4a ff3 fs3 fc0 sc0 ls0 ws0">Verilog HDL provides the following two types of sequential block:</div><div class="t m0 x1 h7 y4b ff8 fs3 fc0 sc0 ls0 ws0"> The always block. This contains sequential statements that execute repetitively, usually in</div><div class="t m0 x2 h5 y4c ff3 fs3 fc0 sc0 ls0 ws0">response to some sort of trigger mechanism. An always block acts rather like a continuous</div><div class="t m0 x2 h5 y4d ff3 fs3 fc0 sc0 ls0 ws0">loop that never terminates. This type of block can be used to describe any type of digital</div><div class="t m0 x2 h5 y4e ff3 fs3 fc0 sc0 ls0 ws0">hardware.</div><div class="t m0 x1 h7 y4f ff8 fs3 fc0 sc0 ls0 ws0"> The initial block. This contains sequential statements that execute from beginning to</div><div class="t m0 x2 h5 y50 ff3 fs3 fc0 sc0 ls1d ws0">end once only, commencing at the start of a simulation run at time zero. Verilog</div><div class="t m0 x2 h5 y51 ff5 fs3 fc0 sc0 ls1d ws0">initial blocks are used almost exclusively in simulation tes t ﬁxtures, usually to create</div><div class="t m0 x2 h5 y52 ff3 fs3 fc0 sc0 ls1e ws0">test input stimuli a nd control the duration of a simulation run. This type o f block is not</div><div class="t m0 x2 h5 y53 ff3 fs3 fc0 sc0 ls22 ws0">generally used to describe synthesizable digital hardware, although a simulation model</div><div class="t m0 x2 h5 y54 ff3 fs3 fc0 sc0 ls24 ws0">may contain an initi al statement to perform an initialization of memory or to load</div><div class="t m0 x2 h5 y55 ff3 fs3 fc0 sc0 ls26 ws0">delay data.</div><div class="t m0 x2 h5 y56 ff3 fs3 fc0 sc0 ls27 ws0">The two types of sequential block described above are, in fact, parallel statements ;</div><div class="t m0 x1 h5 y57 ff3 fs3 fc0 sc0 ls29 ws0">therefore, a module can contain any number of them. The order in which the always and</div><div class="t m0 x1 h5 y58 ff5 fs3 fc0 sc0 ls1d ws0">initial blocks appear within the module does not affect the way in which they execute.</div><div class="t m0 x1 h5 y59 ff3 fs3 fc0 sc0 ls2b ws0">In this sense, a sequential block is similar t o a continuous assignment: the latter uses a</div><div class="t m0 x1 h5 y5a ff3 fs3 fc0 sc0 ls0 ws0">single expression to assign a value to a target whenever a signal on t he right-hand side</div><div class="t m0 x1 h5 y5b ff3 fs3 fc0 sc0 ls29 ws0">undergoes a change, whereas the former executes a sequence of statements in response to</div><div class="t m0 x1 h5 y5c ff3 fs3 fc0 sc0 ls0 ws0">some sort of trigge ring event.</div><div class="t m0 x2 h5 y5d ff3 fs3 fc0 sc0 ls0 ws0">Figure 8.2 shows the syntax of the initial sequential block, along with an example</div><div class="t m0 x1 h5 y5e ff3 fs3 fc0 sc0 ls0 ws0">showing how the construct can be used to generate a clock signal.</div><div class="t m0 x2 h5 y5f ff3 fs3 fc0 sc0 ls0 ws0">As can be seen in lines 3 to 8, an initial block contains a sequence of one or more state-</div><div class="t m0 x1 h5 y60 ff3 fs3 fc0 sc0 ls0 ws0">ments enclosed within a begin...end block. Occasionally, there is only a single statement</div><div class="t m0 x1 h5 y61 ff3 fs3 fc0 sc0 ls0 ws0">enclosed within the initial block; in this case, it is permissible to omit the begin...end</div><div class="t m0 x1 h5 y62 ff3 fs3 fc0 sc0 ls0 ws0">bracketing, as shown in lines 12 and 13. It is recommended, however, that the bracketing is</div><div class="t m0 x1 h5 y63 ff3 fs3 fc0 sc0 ls0 ws0">included, regardless of the number of sequential statements, in order to minimize the possibility</div><div class="t m0 x1 h5 y64 ff3 fs3 fc0 sc0 ls0 ws0">of syntax errors.</div><div class="t m0 x2 h5 y65 ff3 fs3 fc0 sc0 ls0 ws0">Figure 8.2 also includes an example initial block (lines 14 to 21), the purpose of which is</div><div class="t m0 x1 h5 y66 ff3 fs3 fc0 sc0 ls0 ws0">to generate a repetitive clock signal. A local parameter named PERIOD is deﬁned in line 14; this</div><div class="t m0 x1 h5 y67 ff3 fs3 fc0 sc0 ls0 ws0">sets the time period of the clock waveform to 100 time-units. The execution of the initial</div><div class="t m0 x1 h5 y68 ff3 fs3 fc0 sc0 ls0 ws0">block starts at time zero at line 18, where the CLK signal is initializ ed to logic 0; note that the</div><div class="t m0 x1 h5 y69 ff3 fs3 fc0 sc0 ls0 ws0">signal CLK must be declared as a reg, since it must be capable of retaining the value last</div><div class="t m0 x1 h5 y6a ff3 fs3 fc0 sc0 ls0 ws0">assigned to it by statements within the sequential block. Also note that the initializ ation of CLK</div><div class="t m0 xf hf y3f ff11 fs8 fc0 sc0 ls0 ws0">The Behavioural Style of Description: the Sequential Block 199</div></div><div class="pi" data-data='{"ctm":[1.961965,0.000000,0.000000,1.961965,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/bg4.jpg"><div class="t m0 x10 h5 y6b ff3 fs3 fc0 sc0 ls0 ws0">could have been included as part of its declaration in line 15, as shown below:</div><div class="t m0 x7 h7 y6c ff7 fs3 fc0 sc0 ls0 ws0">15 reg CLK ¼ 1'b0;</div><div class="t m0 x7 h5 y6d ff3 fs3 fc0 sc0 ls2e ws0">Following initialization of CLK to logic 0, the next statements to execute within the</div><div class="t m0 x6 h5 y6e ff3 fs3 fc0 sc0 ls31 ws0">initial block are lines 19 and 20 of the listing in Figure 8.2. These contain an</div><div class="t m0 x6 h5 y6f ff4 fs3 fc0 sc0 ls32 ws0">endless loop statement known as a forever loop, having the general syntax shown</div><div class="t m0 x6 h5 y70 ff3 fs3 fc0 sc0 ls32 ws0">below:</div><div class="t m0 x11 h10 y71 ff5 fs3 fc0 sc0 ls0 ws0">forever</div><div class="t m0 x11 h10 y72 ff5 fs3 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x2 h6 y73 ff6 fs3 fc0 sc0 ls0 ws0">//sequential statement 1</div><div class="t m0 x12 h11 y74 ffc fs9 fc0 sc0 ls0 ws0">1</div><div class="t m0 x13 h12 y75 ff13 fsa fc0 sc0 ls33 ws0">//general syntax of the initial sequential block</div><div class="t m0 x12 h11 y76 ffc fs9 fc0 sc0 ls0 ws0">2</div><div class="t m0 x13 h12 y77 ff13 fsa fc0 sc0 ls34 ws5">//containing more than one statement</div><div class="t m0 x12 h11 y78 ffc fs9 fc0 sc0 ls0 ws0">3</div><div class="t m0 x13 h13 y79 ffd fs9 fc0 sc0 ls35 ws0">initial</div><div class="t m0 x12 h11 y7a ffc fs9 fc0 sc0 ls0 ws0">4 begin</div><div class="t m0 x12 h12 y7b ffc fsa fc0 sc0 ls0 ws0">5 //sequential statement 1 </div><div class="t m0 x12 h12 y7c ffc fsa fc0 sc0 ls0 ws0">6 //sequential statement 2 </div><div class="t m0 x12 h11 y7d ffc fs9 fc0 sc0 ls0 ws0">7</div><div class="t m0 x14 h13 y7e ffd fs9 fc0 sc0 ls36 ws0"> ... </div><div class="t m0 x12 h11 y7f ffc fs9 fc0 sc0 ls0 ws0">8 end</div><div class="t m0 x12 h11 y80 ffc fs9 fc0 sc0 ls0 ws0">9</div><div class="t m0 x12 h11 y81 ffc fs9 fc0 sc0 ls0 ws0">10</div><div class="t m0 x13 h12 y82 ff13 fsa fc0 sc0 ls33 ws0">//general syntax of the initial sequential block</div><div class="t m0 x12 h11 y83 ffc fs9 fc0 sc0 ls0 ws0">11 //containing one statement (no need for begin...end)</div><div class="t m0 x12 h11 y84 ffc fs9 fc0 sc0 ls0 ws0">12</div><div class="t m0 x13 h13 y85 ffd fs9 fc0 sc0 ls35 ws0">initial</div><div class="t m0 x12 h12 y86 ffc fsa fc0 sc0 ls34 ws0">13</div><div class="t m0 x13 h12 y87 ff13 fsa fc0 sc0 ls34 ws5"> //sequential statement </div><div class="t m0 x12 h11 y88 ffc fs9 fc0 sc0 ls0 ws0">14</div><div class="t m0 x13 h13 y89 ffd fs9 fc0 sc0 ls37 ws0">localparam</div><div class="t m0 x15 h11 y88 ffc fs9 fc0 sc0 ls38 ws0"> PERIOD = 100; </div><div class="t m0 x16 h12 y8a ff13 fsa fc0 sc0 ls34 ws6">//clock period</div><div class="t m0 x12 h11 y8b ffc fs9 fc0 sc0 ls0 ws0">15 reg CLK;</div><div class="t m0 x12 h11 y8c ffc fs9 fc0 sc0 ls0 ws0">16 initial</div><div class="t m0 x12 h11 y8d ffc fs9 fc0 sc0 ls0 ws0">17</div><div class="t m0 x13 h13 y8e ffd fs9 fc0 sc0 ls36 ws0">begin</div><div class="t m0 x17 h11 y8d ffc fs9 fc0 sc0 ls35 ws7"> </div><div class="t m0 x12 h11 y8f ffc fs9 fc0 sc0 ls3a ws7">18 CLK = 1'b0; </div><div class="t m0 x12 h11 y90 ffc fs9 fc0 sc0 ls0 ws0">19 forever</div><div class="t m0 x18 h11 y91 ff13 fsa fc0 sc0 ls34 ws0">//an endless loop! </div><div class="t m0 x12 h11 y92 ffc fs9 fc0 sc0 ls3c ws8">20 #(PERIOD/2) CLK = ~CLK; </div><div class="t m0 x12 h11 y93 ffc fs9 fc0 sc0 ls0 ws0">21 end</div><div class="t m0 x19 h14 y94 fff fsb fc0 sc0 ls3d ws0">CLK</div><div class="t m0 x1a h14 y95 fff fsb fc0 sc0 ls0 ws0">00105</div><div class="t m0 x1b h14 y96 fff fsb fc0 sc0 ls0 ws0">0</div><div class="t m0 x1c h10 y97 ff10 fs8 fc0 sc0 ls0 ws0">Figure 8.2 Syntax of the initial block and an example.</div><div class="t m0 x6 hf y3f ff1 fs8 fc0 sc0 ls0 ws0">200 Describing Combinational and Sequential Logic using Verilog HDL</div></div><div class="pi" data-data='{"ctm":[1.961965,0.000000,0.000000,1.961965,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6262b4654f8811599ef26720/bg5.jpg"><div class="t m0 x1d h6 y40 ff6 fs3 fc0 sc0 ls0 ws0">//sequential statement 2</div><div class="t m0 x1e h15 y98 ff12 fs3 fc0 sc0 ls2d ws0">...</div><div class="t m0 x1f h10 y99 ff5 fs3 fc0 sc0 ls0 ws0">end</div><div class="t m0 x2 h5 y9a ff3 fs3 fc0 sc0 ls0 ws0">In common with the initi al block itself, the forever loop may contain a single</div><div class="t m0 x1 h5 y9b ff3 fs3 fc0 sc0 ls0 ws0">statement or a number of statements that are required to repeat indeﬁnitely; in the latt er case,</div><div class="t m0 x1 h5 y9c ff3 fs3 fc0 sc0 ls0 ws0">it must include the begin...end bracketing shown above. The example shown in Figure 8.2</div><div class="t m0 x1 h5 y9d ff3 fs3 fc0 sc0 ls0 ws0">contains a single delayed sequential assignment statement in line 20 (the use of the hash symbol</div><div class="t m0 x1 h5 y9e ff3 fs3 fc0 sc0 ls0 ws0"># within a sequential block indicates a time delay). The effect of this statement is to invert the</div><div class="t m0 x1 h5 y9f ff7 fs3 fc0 sc0 ls0 ws0">CLK signal every 50 time-units repetitively; this results in the CLK signal having the waveform</div><div class="t m0 x1 h5 ya0 ff3 fs3 fc0 sc0 ls0 ws0">shown at the bottom of Figure 8.2.</div><div class="t m0 x2 h5 ya1 ff3 fs3 fc0 sc0 ls0 ws0">As it stands, the Verilog description contained in lines 14–21 of Figure 8.2 could present</div><div class="t m0 x1 h5 ya2 ff3 fs3 fc0 sc0 ls0 ws0">a potential problem to a simul ator, in that most such tools have a command to allow the sim-</div><div class="t m0 x1 h5 ya3 ff3 fs3 fc0 sc0 ls0 ws0">ulator to effectively run forever (e.g. ‘run –all’ in Modelsim</div><div class="t m1 x20 h16 ya4 ff14 fsc fc0 sc0 ls0 ws0">1</div><div class="t m0 x21 h5 ya5 ff3 fs3 fc0 sc0 ls0 ws0">). The forever loop in lines</div><div class="t m0 x1 h5 ya6 ff3 fs3 fc0 sc0 ls0 ws0">19 and 20 would cause a simulator to run indeﬁnitely, or at least until the host computer ran out</div><div class="t m0 x1 h5 ya7 ff3 fs3 fc0 sc0 ls0 ws0">of memory to store the huge amount of simulation data generated.</div><div class="t m0 x2 h5 ya8 ff3 fs3 fc0 sc0 ls0 ws0">There are two methods by which the above problem can be solved:</div><div class="t m0 x1 h5 ya9 ff3 fs3 fc0 sc0 ls0 ws0">1. Include an additional initial block containing a $stop system command.</div><div class="t m0 x1 h5 yaa ff3 fs3 fc0 sc0 ls0 ws0">2. Replace the forever loop with a repeat loop.</div><div class="t m0 x1 h5 yab ff3 fs3 fc0 sc0 ls0 ws0">The ﬁrst solution involves adding the following statement:</div><div class="t m0 x1d h6 yac ff6 fs3 fc0 sc0 ls0 ws0">//n is the no. of clock pulses required</div><div class="t m0 x1f h6 yad ff5 fs3 fc0 sc0 ls0 ws0">initial #(PERIOD*n) $stop;</div><div class="t m0 x1 h5 yae ff3 fs3 fc0 sc0 ls0 ws0">The above statement can be inserted anywhere after line 14 within the module containing the</div><div class="t m0 x1 h5 yaf ff3 fs3 fc0 sc0 ls0 ws0">statements shown in Figure 8.2. The execution of the initial block in line 16 commences at the</div><div class="t m0 x1 h5 yb0 ff3 fs3 fc0 sc0 ls0 ws0">same time as the statement shown above (0 s); therefore, the delayed $stop command will</div><div class="t m0 x1 h5 yb1 ff3 fs3 fc0 sc0 ls0 ws0">execute at an absolute time equal to n*PERIOD seconds. The result is a simulation run lasting</div><div class="t m0 x1 h5 yb2 ff3 fs3 fc0 sc0 ls0 ws0">exactly n clock periods. It should be noted that, in order for the above statement to compile</div><div class="t m0 x1 h5 yb3 ff3 fs3 fc0 sc0 ls0 ws0">correctly, the variable n would have to be replaced by an actual positive number or would have to</div><div class="t m0 x1 h5 yb4 ff3 fs3 fc0 sc0 ls0 ws0">have been previously declared as a local parameter.</div><div class="t m0 x2 h5 yb5 ff3 fs3 fc0 sc0 ls0 ws0">The second solution involves modifying the initial block in lines 16–21 of the listing</div><div class="t m0 x1 h5 yb6 ff3 fs3 fc0 sc0 ls0 ws0">given in Figure 8.2 to that shown below:</div><div class="t m0 x2 h6 yb7 ff7 fs3 fc0 sc0 ls0 ws0">1 initial</div><div class="t m0 x2 h6 yb8 ff7 fs3 fc0 sc0 ls0 ws0">2 begin</div><div class="t m0 x2 h7 yb9 ff7 fs3 fc0 sc0 ls0 ws0">3 CLK ¼ 1'b0;</div><div class="t m0 x2 h6 yba ff7 fs3 fc0 sc0 ls0 ws0">4 repeat (n) //an ﬁnite loop</div><div class="t m0 x2 h6 ybb ff7 fs3 fc0 sc0 ls0 ws0">5 begin</div><div class="t m0 x2 h7 ybc ff7 fs3 fc0 sc0 ls0 ws0">6 #(PERIOD/2) CLK ¼ 1'b1;</div><div class="t m0 x2 h7 ybd ff7 fs3 fc0 sc0 ls0 ws0">7 #(PERIOD/2) CLK ¼ 1'b0;</div><div class="t m0 x2 h6 ybe ff7 fs3 fc0 sc0 ls0 ws0">8 end</div><div class="t m0 xf hf y3f ff11 fs8 fc0 sc0 ls0 ws0">The Behavioural Style of Description: the Sequential Block 201</div></div><div class="pi" data-data='{"ctm":[1.961965,0.000000,0.000000,1.961965,0.000000,0.000000]}'></div></div>