miaobiao2.rar

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:48:49 12/03/2012 // Design Name: // Module Name: miaobiao // Project Name: // Target Devices: // Tool versions: F // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module miaobiao(clk,reset,start,an,a_to_g,dp ); input clk,reset,start; output [3:0]an; output [6:0]a_to_g; output dp; wire start,clk,reset; reg a_to_g; reg [3:0]an; reg dp; reg [3:0]one,two,three,four; reg clk100hz; reg zhuangtai; reg c1,c2,c3; reg [1:0]state,nextstate; reg digit; reg clk1khz,clk5000hz; //分频// integer count1,count2,count3; parameter s1 = 2'b00, //用独热码表示状态变量； s2 = 2'b01, s3 = 2'b10, s4 = 2'b11; always @(posedge clk or posedge reset) begin if(reset) begin count1<=1; clk100hz <=0; end else begin if(count1==500000) begin count1<=1; end else begin if (count1<250000) begin clk100hz<=0; end else begin clk100hz<=1; end count1<=count1+1; end end end //计时// //10ms// always @(posedge clk100hz or posedge reset ) begin if(reset) begin one<=4'b0000; c1<=1'b0; end else begin if(zhuangtai==1'b1) begin if(one==4'b1001) begin one<=4'b0000; c1<=1'b1; end else begin one<=one+4'b0001; c1<=1'b0; end end else begin one<=one; end end end //100ms// always@(posedge c1 or posedge reset) begin if(reset==1) begin two<=4'b0000; c2<= 1'b0; end else begin if(two==4'b1001) begin two<=4'b0000; c2<=1'b1; end else begin two<=two+1; c2<=1'b0; end end end //1s// always@(posedge c2 or posedge reset) begin if(reset==1) begin three<=4'b0000; c3<=1'b0; end else begin if(three==4'b1001) begin three<=4'b0000; c3<=1'b1; end else begin three<=three+1; c3<=1'b0; end end end //10s// always@(posedge c3 or posedge reset) begin if(reset==1) begin four<=4'b0000; end else begin if(four==4'b0101) begin four<=4'b0000; end else begin four<=four+1; end end end //显示// always@(posedge clk or posedge reset) begin if(reset) begin count2<=1; end else begin if(count2==10000) begin count2<=1; end else begin count2<=count2+1; if(count2>5000) begin clk5000hz<=1'b1; end else begin clk5000hz<=1'b0; end end end end always begin dp<=1'b1; end always@(posedge clk5000hz or posedge reset ) begin if(reset) begin an<=4'b1110; end else begin an<={an[2:0],an[3]}; end end always @(*) begin case(an) 4'b0111:digit<=four; 4'b1011:digit<=three; 4'b1101:digit<=two; 4'b1110:digit<=one; default:digit<=4'b0000; endcase end always@(digit) begin case(digit) 4'b0000:a_to_g<=7'b0000001; 4'b0001:a_to_g<=7'b1001111; 4'b0010:a_to_g<=7'b0010010; 4'b0011:a_to_g<=7'b0000110; 4'b0100:a_to_g<=7'b1001100; 4'b0101:a_to_g<=7'b0100100; 4'b0110:a_to_g<=7'b0100000; 4'b0111:a_to_g<=7'b0001111; 4'b1000:a_to_g<=7'b0000000; 4'b1001:a_to_g<=7'b0000100; default: a_to_g<=7'b111111;//不显示// endcase end //分频// always@(posedge clk) begin if(reset) begin count3<=1; end else begin if(count3==50000) begin count3<=1'b1; end else begin count3<=count3+1; if(count3<25000) begin clk1khz<=1'b1; end else begin clk1khz<=1'b0; end end end end //按键状态机// always@(posedge clk1khz or posedge reset) begin if(reset) begin state<=4'b0001; end else begin state<=nextstate; end end always@(state,start) begin case(state) s1:begin zhuangtai<=1'b0; if(start==1'b1) begin nextstate<=s2; end else begin nextstate<=s1; end end s2:begin zhuangtai<=1'b0; if(start==1'b1) begin nextstate<=s2; end else begin nextstate<=s3; end end s3:begin zhuangtai<=1'b1; if(start==1'b1) begin nextstate<=s4; end else begin nextstate<=s3; end end s4:begin zhuangtai<=1'b1; if(start==1'b1) begin nextstate<=s4; end else begin nextstate<=s1; end end default:begin zhuangtai<=1'b0; nextstate<=s1; end endcase end endmodule