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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622ba43e15da9b288b070745/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">European Journal of Scientific Research </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">ISSN 1450-216X Vol.83 No.1 (2012), pp.39-52 </div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls1 ws1">© EuroJournals Publishing, Inc. 2012 </div><div class="t m0 x1 h2 y4 ff1 fs0 fc1 sc0 ls2 ws2">http://www.europeanjournalo<span class="ls1">fscientificresearch.com </span></div><div class="t m0 x2 h3 y5 ff1 fs1 fc0 sc0 ls3 ws2"> </div><div class="t m0 x3 h4 y6 ff2 fs1 fc0 sc0 ls4 ws3">Area and Power Efficient Hybrid PTCSL MUX Design </div><div class="t m0 x2 h2 y7 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x2 h2 y8 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x4 h5 y9 ff2 fs0 fc0 sc0 ls0 ws0">S. Vijayakumar </div><div class="t m0 x5 h6 ya ff3 fs0 fc0 sc0 ls4 ws4">Department of Electronics <span class="ls1 ws5">and Communication Engineering </span></div><div class="t m0 x6 h6 yb ff3 fs0 fc0 sc0 ls2 ws6">Ganadipathy Tulsi’s Jain Engineering College, Vellore </div><div class="t m0 x7 h6 yc ff3 fs0 fc0 sc0 ls3 ws2">Tamil Nadu, India – 632102 </div><div class="t m0 x8 h2 yd ff1 fs0 fc0 sc0 ls5 ws7">E-mail: vijaysuresh1975@yahoo.com </div><div class="t m0 x9 h2 ye ff1 fs0 fc0 sc0 ls3 ws2">Tel: +91-9994238301 </div><div class="t m0 x2 h2 yf ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 xa h5 y10 ff2 fs0 fc0 sc0 ls3 ws2">Reeba Korah </div><div class="t m0 x5 h6 y11 ff3 fs0 fc0 sc0 ls4 ws4">Department of Electronics <span class="ls1 ws5">and Communication Engineering </span></div><div class="t m0 xb h6 y12 ff3 fs0 fc0 sc0 ls6 ws8">St. Joseph’s College of Engineer<span class="ls2 ws9">ing, Chennai, Tamil Nadu, India – 600119 </span></div><div class="t m0 xc h2 y13 ff1 fs0 fc0 sc0 ls7 ws6">E-mail: reeba26in@gm<span class="_ _0"></span>ail.com </div><div class="t m0 x9 h2 y14 ff1 fs0 fc0 sc0 ls3 ws2">Tel: +91-9176630973 </div><div class="t m0 x2 h7 y15 ff1 fs2 fc0 sc0 ls3 ws2"> </div><div class="t m0 x2 h7 y16 ff1 fs2 fc0 sc0 ls3 ws2"> </div><div class="t m0 xd h5 y17 ff2 fs0 fc0 sc0 ls8 ws2">Abstract </div><div class="t m0 x1 h2 y18 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 xe h2 y19 ff1 fs0 fc0 sc0 ls9 wsa">Multiplexer (MUX) is the most popular de<span class="ls2 wsb">sign which is well known to all as a </span></div><div class="t m0 xf h2 y1a ff1 fs0 fc0 sc0 lsa wsc">switch. It consumes considerable portions of<span class="ls0 wsd"> power among the blocks of an ALU which is </span></div><div class="t m0 xf h2 y1b ff1 fs0 fc0 sc0 ls5 wse">the heart of any digital design right from <span class="lsb wsf">a large super computer to a small gadget. </span></div><div class="t m0 xf h2 y1c ff1 fs0 fc0 sc0 ls9 ws10">Different approaches exist to optimize the MUX by m<span class="_ _0"></span>eans of power, area and speed. The </div><div class="t m0 xf h2 y1d ff1 fs0 fc0 sc0 ls2 ws11">comparison of area between conventional MUX,<span class="ls4 ws12"> com<span class="_ _0"></span>bination of transmission gate and </span></div><div class="t m0 xf h2 y1e ff1 fs0 fc0 sc0 ls3 ws13">static method as a hybrid style, transmission ga<span class="lsc ws14">te logic style are pres<span class="ls8 ws15">ented in this paper. </span></span></div><div class="t m0 xf h2 y1f ff1 fs0 fc0 sc0 lsd ws16">The TGCSL MUX consumes nearly 20% lower <span class="_ _0"></span><span class="ls4 ws17">power than the other two styles (C2MOS, </span></div><div class="t m0 xf h2 y20 ff1 fs0 fc0 sc0 ls4 ws18">TGL) at VDD < 1V. Though the TGL MUX operat<span class="ls3 ws19">es with less power than the other two </span></div><div class="t m0 xf h2 y21 ff1 fs0 fc0 sc0 ls3 ws1a">logic styles, it fails to produ<span class="ls2 ws1b">ce full swing. This is a great<span class="ls0 ws1c"> impact which affects the </span></span></div><div class="t m0 xf h2 y22 ff1 fs0 fc0 sc0 ls9 ws1d">performance of a larger<span class="_ _0"></span> de-composed multiple<span class="_ _0"></span>xer tree with TGL MUX. Finally the area </div><div class="t m0 xf h2 y23 ff1 fs0 fc0 sc0 ls0 ws0">comparison is also given to conclude that<span class="ls3 ws1e"> the proposed method <span class="lsa ws1f">is a better choice. </span></span></div><div class="t m0 xf h8 y24 ff1 fs3 fc0 sc0 ls3 ws2"> </div><div class="t m0 xf h8 y25 ff1 fs3 fc0 sc0 ls3 ws2"> </div><div class="t m0 xf h2 y26 ff2 fs0 fc0 sc0 ls6 ws2">Keywords:<span class="ff1 ls4 ws20"> <span class="_ _1"> </span>Mixed MUX, Transmission gate – Sta<span class="ls1 ws21">tic, Ultra Low Power, Hybrid, Area </span></span></div><div class="t m0 x10 h2 y27 ff1 fs0 fc0 sc0 lsd ws9">Optimization, Arithm<span class="_ _0"></span>etic Core </div><div class="t m0 x1 h2 y28 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x1 h9 y29 ff2 fs4 fc0 sc0 lse ws22">1. Introduction </div><div class="t m0 x1 h2 y2a ff1 fs0 fc0 sc0 ls6 ws23">Multiplexer (MUX) is fundamentally used as a switc<span class="ls9 ws24">h in arithmetic circu<span class="_ _0"></span>its. ALU is the dominant </span></div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 lsf ws25">hardware element widely from handhelds to big co<span class="_ _0"></span><span class="ls6 ws26">mputing devices. A digital equipment as a big unit </span></div><div class="t m0 x1 h2 y2c ff1 fs0 fc0 sc0 lsc ws27">has its market which depends on power back-up. Wh<span class="lsa ws28">en the size influences, it causes the power to </span></div><div class="t m0 x1 h2 y2d ff1 fs0 fc0 sc0 ls2 ws29">proportionally vary. The increased power back-up time <span class="lsb ws2a">for the handheld devices is an im<span class="_ _0"></span>portant factor </span></div><div class="t m0 x1 h2 y2e ff1 fs0 fc0 sc0 ls4 ws2b">which always increases the expectations of the <span class="ws2c">consumers for lower power consumption. Apart from </span></div><div class="t m0 x1 h2 y2f ff1 fs0 fc0 sc0 ls10 ws8">that, the sub-threshold activ<span class="_ _0"></span>ities play a lead role in<span class="lsa ws1e"> a circuit design approach. <span class="_ _0"></span><span class="ls10 ws2d">The careful balance to run<span class="_ _0"></span> </span></span></div><div class="t m0 x1 h2 y30 ff1 fs0 fc0 sc0 ls9 ws2e">a system at low power but with reduced second order e<span class="ls8 ws2f">ffects [1] is the important <span class="ls4 ws3">criteria to be governed </span></span></div><div class="t m0 x1 h2 y31 ff1 fs0 fc0 sc0 ls9 ws30">in parallel. The control of power <span class="ls11 ws31">consumed by multiplexers<span class="_ _0"></span> is the key factor to meet the backup tim<span class="_ _0"></span>e </span></div><div class="t m0 x1 h2 y32 ff1 fs0 fc0 sc0 ls5 ws2">requirements. </div><div class="t m0 x11 h2 y33 ff1 fs0 fc0 sc0 ls5 ws32">Meanwhile, the data length is increasing which is<span class="lsa ws33"> of at least 64 bits nowadays. When the MUX </span></div><div class="t m0 x1 h2 y34 ff1 fs0 fc0 sc0 ls11 ws34">is used as a switch for such circuit then the entire<span class="_ _0"></span><span class="lsf ws35"> sub-cells will consume power<span class="_ _0"></span><span class="lsb ws36">. Perhaps all the cells in </span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622ba43e15da9b288b070745/bg2.jpg"><div class="t m0 x12 h2 y1 ff1 fs0 fc0 sc0 ls3 ws37">Area and Power Efficient Hybrid PTCSL MUX Design <span class="_ _2"> </span>40 </div><div class="t m0 x12 h2 y35 ff1 fs0 fc0 sc0 ls12 ws38">a design are not used to propagate<span class="lsd ws39"> the data which is the nota<span class="_ _0"></span>ble factor to reduce the<span class="_ _0"></span> power. Hence the </span></div><div class="t m0 x12 h2 y36 ff1 fs0 fc0 sc0 lsa ws3a">MUX in a data path with more bits repla<span class="_ _0"></span>ced by <span class="ls6 ws3b">2-1 MUX as a tree is called decomposition<span class="_ _0"></span> [2] which </span></div><div class="t m0 x12 h2 y37 ff1 fs0 fc0 sc0 ls5 ws3c">can be a better solution to avoid unnecessary power. <span class="_ _0"></span><span class="lsa ws34">There are different approaches followed for power </span></div><div class="t m0 x12 h2 y38 ff1 fs0 fc0 sc0 ls6 ws3d">optimization in a decomposed MUX tree.<span class="_ _0"></span> The comm<span class="ls5 ws3e">on idea is to reduce the power consumption and </span></div><div class="t m0 x12 h2 y39 ff1 fs0 fc0 sc0 lsf ws3f">increase the speed. </div><div class="t m0 x13 h2 y3a ff1 fs0 fc0 sc0 lsa ws40">Different papers approach th<span class="ls13 ws41">e MUX using CMOS pass transist<span class="ls7 ws42">or to realize the required<span class="_ _0"></span> </span></span></div><div class="t m0 x12 h2 y3b ff1 fs0 fc0 sc0 ls2 ws43">function with their own pros and cons. Particularly <span class="ls1 ws44">the trade-off always exis<span class="ls14 ws45">ts between supply voltage, </span></span></div><div class="t m0 x12 h2 y3c ff1 fs0 fc0 sc0 ls5 ws46">current, power, area and delay. Some performance crite<span class="ls15 ws47">ria need to be m<span class="_ _0"></span>et at the same time with a </span></div><div class="t m0 x12 h2 y3d ff1 fs0 fc0 sc0 ls16 ws2">comp<span class="_ _3"></span>ro<span class="_ _3"></span>mise<span class="_ _3"></span>. </div><div class="t m0 x13 h2 y3e ff1 fs0 fc0 sc0 ls3 ws48">Unique techniques have been pr<span class="ls17 ws49">oposed to reduce th<span class="ls8 ws4a">e power consumption of MUX trees. Power </span></span></div><div class="t m0 x12 h2 y3f ff1 fs0 fc0 sc0 ls5 ws4b">reduction in a MUX tree at algorithmic level is proposed<span class="ls2 ws4c"> in [2]-[4] while the ci<span class="ls4 ws4d">rcuit level is given in </span></span></div><div class="t m0 x12 h2 y40 ff1 fs0 fc0 sc0 ls13 ws4e">[5]-[6]. Numerous circuit <span class="ls4 ws4f">design approaches are available to build a 2-1 MUX tree. However, to obtain </span></div><div class="t m0 x12 h2 y41 ff1 fs0 fc0 sc0 ls5 ws50">the power optimization it is required to use th<span class="lsf ws51">e pr<span class="_ _0"></span>oper MUX structure to complete the task. </span></div><div class="t m0 x13 h2 y42 ff1 fs0 fc0 sc0 ls3 ws52">Feeding the power to non-portabl<span class="lsb ws53">e applications is easier than<span class="_ _0"></span> the one for portable ne<span class="_ _0"></span>eds which </span></div><div class="t m0 x12 h2 y43 ff1 fs0 fc0 sc0 ls9 ws54">is critical to achieve at low power with reduced <span class="ls2 ws55">leakage. It happens due to scaling down the device </span></div><div class="t m0 x12 h2 y44 ff1 fs0 fc0 sc0 ls2 ws56">(technology scaling). The reduced dim<span class="_ _0"></span>ension of such device causes <span class="ls10 ws57">the property of the m<span class="_ _0"></span>aterial </span></div><div class="t m0 x12 h2 y45 ff1 fs0 fc0 sc0 ls5 ws58">involved in it to become more complex. Hence designe<span class="ls3 ws59">rs give preference to a logic style which ensures </span></div><div class="t m0 x12 h2 y46 ff1 fs0 fc0 sc0 lsf ws19">a number of factors to be sacrificed rather than sa<span class="ls0 ws5a">tisfied. This is because of the trade-off discussed a </span></div><div class="t m0 x12 h2 y47 ff1 fs0 fc0 sc0 lsa ws5b">short while. For this reason, the power reduction met<span class="ws5c">hods are approached and analyzed in this paper </span></div><div class="t m0 x12 h2 y48 ff1 fs0 fc0 sc0 ls3 ws5d">than the delay. The Complementary Static CMOS<span class="_ _0"></span><span class="ls4 ws5e"> (C2MOS), Transmission Gate Logic (TGL) and </span></div><div class="t m0 x12 h2 y49 ff1 fs0 fc0 sc0 ls0 ws5f">Transmission Gate – Complem<span class="_ _0"></span>entary Static Logi<span class="ws60">c (TGCSL) as a hybrid method are taken for the </span></div><div class="t m0 x12 h2 y4a ff1 fs0 fc0 sc0 lsa ws61">comparison of power, delay and area among the three designs. </div><div class="t m0 x13 h2 y4b ff1 fs0 fc0 sc0 ls5 ws62">The various technology impacts which play vital <span class="ws63">role in a design are discussed in Section 2. </span></div><div class="t m0 x12 h2 y4c ff1 fs0 fc0 sc0 ls0 ws64">Such factors are responsible for <span class="ls9 ws65">the power consumption, delay and ar</span>ea. The second order effects are </div><div class="t m0 x12 h2 y4d ff1 fs0 fc0 sc0 ls0 ws66">given in section 3. The next sect<span class="ls10 ws67">ion states the<span class="_ _0"></span> power dissipation.<span class="_ _0"></span> <span class="lsc ws68">Section 5 describes the functional </span></span></div><div class="t m0 x12 h2 y4e ff1 fs0 fc0 sc0 lsa ws69">representations of the Compleme<span class="ls6 ws6a">ntary CMOS (C2MOS), Transm<span class="_ _0"></span>i<span class="ls2 ws6b">ssion Gate (TGL) and the hybrid </span></span></div><div class="t m0 x12 h2 y4f ff1 fs0 fc0 sc0 lsa ws6c">Transmission Gate – Complem<span class="_ _0"></span>entary Static Logi<span class="ls12 ws6d">c (TGCSL) MUX styles. The simulation setup and </span></div><div class="t m0 x12 h2 y50 ff1 fs0 fc0 sc0 ls9 ws6e">performance evaluations are available in sectio<span class="_ _0"></span>n <span class="ls2 ws6f">6. It includes the comparison of power and delay </span></div><div class="t m0 x12 h2 y51 ff1 fs0 fc0 sc0 ls3 ws70">between them. The factors to be <span class="ls4 ws71">considered for a physical design of<span class="ws72"> a module are given in the next </span></span></div><div class="t m0 x12 h2 y52 ff1 fs0 fc0 sc0 ls4 ws73">section along with the layout impl<span class="ws74">ementations of the mentioned MUX <span class="_ _0"></span><span class="ws75">structures including comparison. </span></span></div><div class="t m0 x12 h2 y53 ff1 fs0 fc0 sc0 ls2 ws1e">Finally the work is concluded in section 8. </div><div class="t m0 x12 h2 y54 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x12 h2 y55 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x12 h9 y56 ff2 fs4 fc0 sc0 ls18 ws76">2. Technology Impacts </div><div class="t m0 x12 h2 y57 ff1 fs0 fc0 sc0 ls5 ws77">Different logic families have their own advantages<span class="lsd ws78"> and drawbacks. Among them, the gain from<span class="_ _0"></span> one </span></div><div class="t m0 x12 h2 y58 ff1 fs0 fc0 sc0 ls0 ws79">style is a draw back with the other style and<span class="_ _0"></span> vice-ve<span class="ls3 ws7a">rsa. It is because of th</span>e discussed tradeoff between </div><div class="t m0 x12 h2 y59 ff1 fs0 fc0 sc0 lsd ws7b">the electrical parameters<span class="_ _0"></span> which are unable to be satis<span class="_ _0"></span><span class="lsa ws7c">fied at the same time as discussed in the previous </span></div><div class="t m0 x12 h2 y5a ff1 fs0 fc0 sc0 lsa ws7d">section. Hence a desired logic styl<span class="ls2 ws7e">e appropriate for a specific functi<span class="_ _0"></span><span class="ls8 ws7f">on may not be suitable for another </span></span></div><div class="t m0 x12 h2 y5b ff1 fs0 fc0 sc0 ls2 ws2">one. </div><div class="t m0 x13 h2 y5c ff1 fs0 fc0 sc0 ls2 ws80">Choices between Static versus dynamic impl<span class="ls0 ws81">ementations, pass-gate versus Conventional </span></div><div class="t m0 x12 h2 y5d ff1 fs0 fc0 sc0 ls2 ws82">CMOS logic styles and synchronous ve<span class="ls4 ws83">rsus asynchronous logic are some <span class="ls5 ws84">of the options available to be </span></span></div><div class="t m0 x12 h2 y5e ff1 fs0 fc0 sc0 lsa ws85">considered. At another level, ther<span class="ls2 ws86">e are also various architectural/str<span class="ls10 ws87">uctu<span class="_ _0"></span>ral choices for implem<span class="_ _0"></span>enting a </span></span></div><div class="t m0 x12 h2 y5f ff1 fs0 fc0 sc0 ls4 ws17">given structure. In this <span class="ws52">section, the trade-offs with respect to <span class="ls2 ws88">low-power design between a selected set </span></span></div><div class="t m0 x12 h2 y60 ff1 fs0 fc0 sc0 ls9 ws89">of circuit approaches will be in<span class="ls8 ws8a">troduced, followed by a discussion of <span class="ls4 ws4d">som<span class="_ _0"></span>e general issues and factors </span></span></div><div class="t m0 x12 h2 y61 ff1 fs0 fc0 sc0 lsc ws8b">affecting the choice of the logic fa<span class="ls7 ws8c">mily. It leads to re-e<span class="ls0 ws8d">ngineer a logic style a<span class="ls4 ws8e">nd produces a new method </span></span></span></div><div class="t m0 x12 h2 y62 ff1 fs0 fc0 sc0 ls4 ws3">to overcome the drawback of a regular style. </div><div class="t m0 x12 h2 y63 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x12 h5 y64 ff2 fs0 fc0 sc0 lsa ws8f">2.1. Low Power Design Factors </div><div class="t m0 x12 h2 y65 ff1 fs0 fc0 sc0 ls11 ws90">Numerous factors are to be consid<span class="_ _0"></span><span class="ls1 ws91">ered for low operating power which le<span class="lsf ws35">ads to different kinds of circuit </span></span></div><div class="t m0 x12 h2 y66 ff1 fs0 fc0 sc0 ls10 ws92">design approaches. It results in iden<span class="_ _0"></span>tifying the suita<span class="ls14 ws93">ble logic style which beha<span class="ls2 ws94">ves as a low power MUX </span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622ba43e15da9b288b070745/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls2 ws95">41 <span class="_ _4"> </span>S. Vijayakumar and Reeba Korah </div><div class="t m0 x1 h2 y35 ff1 fs0 fc0 sc0 lsf ws96">structure. All the parameters taken for consideration ar<span class="_ _0"></span>e used to analyze the three major logic styles<span class="_ _0"></span>: </div><div class="t m0 x1 h2 y36 ff1 fs0 fc0 sc0 ls5 ws97">static, dynamic and pass transistor. The prime objectiv<span class="lsa ws98">e is to com<span class="_ _0"></span>pare the power, delay and area of the </span></div><div class="t m0 x1 h2 y37 ff1 fs0 fc0 sc0 lsa ws99">different styles of MUX design. From the experimental results, the design with the best characteristics </div><div class="t m0 x1 h2 y38 ff1 fs0 fc0 sc0 lsf ws5">will be identified. The design metrics ar<span class="lsb ws9a">e giv<span class="_ _0"></span>en in the following sub-sectio<span class="_ _0"></span>ns. </span></div><div class="t m0 x1 h2 y39 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x1 h5 y67 ff2 fs0 fc0 sc0 ls1 ws1">2.1.1. Supply voltage </div><div class="t m0 x1 h2 y3b ff1 fs0 fc0 sc0 ls9 ws9b">Most of the power consumed by the switching ac<span class="ls4 ws9c">tivity of any circuit is known as dynamic power. </span></div><div class="t m0 x1 h2 y3c ff1 fs0 fc0 sc0 ls4 ws3">Dynamic power in digital CMOS circ<span class="ls0 ws2d">uits is proportional to the square<span class="ls1 ws1"> of the supply voltage given as, </span></span></div><div class="t m0 x11 h6 y3d ff3 fs0 fc0 sc0 ls19 ws2">P <span class="ff4 ls3">α<span class="ff3"> V</span></span></div><div class="t m0 xe ha y68 ff3 fs5 fc0 sc0 ls1a ws2">DD</div><div class="t m0 x14 ha y69 ff3 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m0 x15 h6 y3d ff3 fs0 fc0 sc0 ls3 ws2">ƒ</div><div class="t m0 x16 ha y68 ff3 fs5 fc0 sc0 ls1b ws2">clk</div><div class="t m0 x17 h2 y3d ff1 fs0 fc0 sc0 ls3 ws2"> <span class="_ _5"> </span><span class="ls1c">(1) </span></div><div class="t m0 x11 h2 y3e ff1 fs0 fc0 sc0 lsf ws9d">So the designers try to <span class="ls12 ws9e">find the means of reducing <span class="ff3 ls3 ws2">V</span></span></div><div class="t m0 x18 ha y6a ff3 fs5 fc0 sc0 ls1a ws2">DD</div><div class="t m0 x19 h2 y3e ff1 fs0 fc0 sc0 ls12 ws9f">. However, reduction of <span class="ff3 ls3 ws2">V</span></div><div class="t m0 x1a ha y6a ff3 fs5 fc0 sc0 ls1a ws2">DD</div><div class="t m0 x1b h2 y3e ff1 fs0 fc0 sc0 lsa wsa0"> leads to </div><div class="t m0 x1 h2 y3f ff1 fs0 fc0 sc0 lsa wsa1">worse speed performance, especially when <span class="_ _0"></span><span class="ff3 ls3 ws2">V</span></div><div class="t m0 x1c ha y6b ff3 fs5 fc0 sc0 ls1a ws2">DD</div><div class="t m0 x1d h2 y3f ff1 fs0 fc0 sc0 ls3 ws2"> <span class="_ _3"></span><span class="ff4">≤<span class="_ _3"></span><span class="ff3 ls1d"> V</span></span></div><div class="t m0 x1e ha y6b ff3 fs5 fc0 sc0 ls1e ws2">Tp</div><div class="t m0 x1f h6 y3f ff3 fs0 fc0 sc0 ls2 ws2">+V</div><div class="t m0 x20 ha y6b ff3 fs5 fc0 sc0 ls1e ws2">Tn</div><div class="t m0 x21 h2 y3f ff1 fs0 fc0 sc0 ls10 ws99">. Techniques are then required to reduce th<span class="_ _0"></span>e </div><div class="t m0 x1 h2 y40 ff1 fs0 fc0 sc0 ls9 wsa2">critical paths. These techniques are <span class="lsb wsa3">necessary at every level from<span class="_ _0"></span> algor<span class="ls11 wsa4">ithm and architec<span class="_ _0"></span>ture to circuit, </span></span></div><div class="t m0 x1 h2 y41 ff1 fs0 fc0 sc0 ls0 ws8">device and technology levels. </div><div class="t m0 x1 h2 y42 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x1 h5 y6c ff2 fs0 fc0 sc0 ls5 ws7">2.1.2. Switching Activity </div><div class="t m0 x1 h2 y44 ff1 fs0 fc0 sc0 lsa wsa5">A node does not necessarily make transitions in ever<span class="ls9 wsa6">y cloc<span class="_ _0"></span>k cycle. It depends on the nature of the </span></div><div class="t m0 x1 h2 y45 ff1 fs0 fc0 sc0 ls4 wsa7">circuit, the type of processing that <span class="lsd wsa8">it is carrying out and the statistics of<span class="_ _0"></span> the signals that the circuit is </span></div><div class="t m0 x1 h2 y46 ff1 fs0 fc0 sc0 ls3 wsa9">processing. The average number of da<span class="ls4 wsaa">ta transitions per clock cycle is<span class="ls6 wsab"> called the switch</span></span>ing activity. The </div><div class="t m0 x1 h2 y47 ff1 fs0 fc0 sc0 ls0 wsac">switching activity is a function of the nature and the <span class="lsa wsc">statistics of the input signals. If the inputs do not </span></div><div class="t m0 x1 h2 y48 ff1 fs0 fc0 sc0 ls6 wsad">change within a time period, no switching will occur and hence <span class="ff3 ls3 ws2">a=</span><span class="ls0 wsae">0, which leads to a zero dynam<span class="_ _0"></span>ic </span></div><div class="t m0 x1 h2 y49 ff1 fs0 fc0 sc0 ls0 ws0">power dissipation. </div><div class="t m0 x11 h2 y4a ff1 fs0 fc0 sc0 ls1 wsaf">The switching activity is also strongly dependent on the circuit <span class="lsa wsb0">style (dynamic or static), the </span></div><div class="t m0 x1 h2 y4b ff1 fs0 fc0 sc0 lsa wsb1">function being implemented and the circuit structure used. Unnecessary power consumption due to the </div><div class="t m0 x1 h2 y4c ff1 fs0 fc0 sc0 lsa wsb2">presence of spurious transitions (hazards or g<span class="wsb3">litches) happens since the method of the circuit </span></div><div class="t m0 x1 h2 y4d ff1 fs0 fc0 sc0 lsf ws35">construction. For example, the switching activity in <span class="_ _0"></span><span class="ls9 wsb4">dynamic CMOS logic is high because of the circuit </span></div><div class="t m0 x1 h2 y4e ff1 fs0 fc0 sc0 ls4 wsb5">is pre-charged and discharged every clock cycle when<span class="_ _0"></span><span class="ls9 wsb6"> the output is low. This occurs ev<span class="_ _0"></span>en when the </span></div><div class="t m0 x1 h2 y4f ff1 fs0 fc0 sc0 ls9 wsb7">signals driving the gate are unchanged. On the othe<span class="ls2 wsb8">r hand, with the static CMOS the switching activity </span></div><div class="t m0 x1 h2 y50 ff1 fs0 fc0 sc0 ls2 ws61">depends entirely on the statistics of the input<span class="ls1 wsb9"> signals and, hence, can be high or low. </span></div><div class="t m0 x1 h2 y51 ff1 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x1 h5 y6d ff2 fs0 fc0 sc0 ls0 ws0">2.1.3. Physical Capacitance </div><div class="t m0 x1 h2 y53 ff1 fs0 fc0 sc0 ls1 wsba">The dynamic power dissipation is directly proportiona<span class="ls6 wsbb">l to the physical capacitanc<span class="lsa wsbc">e of the circuit. This </span></span></div><div class="t m0 x1 h2 y54 ff1 fs0 fc0 sc0 ls5 wsbd">physical capacitance comes from the <span class="_ _0"></span><span class="lsa wsbe">transistor parasitic capacitance an<span class="ls1 wsbf">d the interconnect capacitance. </span></span></div><div class="t m0 x1 h2 y55 ff1 fs0 fc0 sc0 ls4 wsc0">A typical CMOS transistor capacitance is shown <span class="wsc1">in figure 1. It can be <span class="ls2 wsc2">reduced by many techniques </span></span></div><div class="t m0 x1 h2 y6e ff1 fs0 fc0 sc0 ls5 wsc3">such as using less logic, smaller transistors, fe<span class="lsf wsc4">wer and shorter wires wherever possible and so on. </span></div><div class="t m0 x1 h2 y6f ff1 fs0 fc0 sc0 ls5 wsc5">Numerous techniques have been <span class="ls4 wsc6">proposed at all design levels su<span class="wsc7">ch as resource sharing, logic </span></span></div><div class="t m0 x1 h2 y70 ff1 fs0 fc0 sc0 ls3 wsc8">minimization, common sub-expression extraction etc. <span class="ls0 wsc9">However, it may not be possible to reduce the </span></div><div class="t m0 x1 h2 y71 ff1 fs0 fc0 sc0 ls5 wsca">capacitance arbitrarily because this <span class="wscb">can lead to undesirable results. </span></div><div class="t m0 x11 h2 y72 ff1 fs0 fc0 sc0 ls6 wscc">For example, reducing transistor sizes implies le<span class="ls0 wscd">ss physical capacitance, <span class="_ _0"></span><span class="ls14 wsce">but results in reducing </span></span></div><div class="t m0 x1 h2 y73 ff1 fs0 fc0 sc0 ls10 wscf">the current driving capability at the same tim<span class="_ _0"></span>e <span class="ls9 wsd0">and this leads to a performance loss. Reduced </span></div><div class="t m0 x1 h2 y74 ff1 fs0 fc0 sc0 ls9 wsd1">performance is often unacceptable but even then, it <span class="_ _0"></span><span class="lsf wsd2">is usually more desirable to<span class="_ _0"></span> scale the supply </span></div><div class="t m0 x1 h2 y75 ff1 fs0 fc0 sc0 ls4 ws83">voltage since this contributes to power dissipation quadr<span class="ls6 wsd3">atically. The overall conclusion is that it is not </span></div><div class="t m0 x1 h2 y76 ff1 fs0 fc0 sc0 lsb wsd4">possible to optimize these f<span class="_ _0"></span>actors independently and a detailed exam<span class="_ _0"></span>ination of the complete solution is </div><div class="t m0 x1 h2 y77 ff1 fs0 fc0 sc0 ls4 ws3">required to ensure that the grea<span class="ls2 ws95">test power benefits are obtained. </span></div><div class="t m0 x1 hb y78 ff1 fs6 fc0 sc0 ls3 ws2"> </div><div class="t m0 x22 h8 y79 ff2 fs3 fc0 sc0 ls1f wsd5">Figure 1:<span class="ff1 ls20 wsd6"> Physical CMOS capacitance </span></div><div class="t m0 x1 hb y7a ff1 fs6 fc0 sc0 ls3 ws2"> </div><div class="t m0 x23 h2 y7b ff1 fs0 fc0 sc0 ls3 ws2"> </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
