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  • 2006-09-16 21:29
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这个是vxworks powerpc bsp与ucos的移植,很经典的!
vxworks0108.rar
内容介绍
/* sysLib.c - SBS Technologies VG4 board system-dependent library */ /* includes */ #include "vxWorks.h" #include "type.h" #include "string.h" #include "vme.h" /* Architecture-dependent includes */ #include "sysLib.h" #include "sysLibExt.h" #include "config.h" #include "ppc750.h" #include "sysL2BackCache.h" #include "pciConfigLib.h" #include "vg4.h" #include "universe.h" #include "mpc107.h" #include "vmlib.h" #include "ivppc.h" #include "esf.h" #ifdef INCLUDE_END # include "endLib.h" #endif /* defines */ #define ZERO 0 #define SYS_MODEL "VG4 " #define SYSMODEL_LEN 80 /* length for sysModelStr string */ #define SYSINFO_LEN 300 /* length for sysInfoStr string */ #define SYSPRODINFO_LEN 300 /* length for sysProdInfoStr string */ /* Macro to read/write a longword to PCI bus */ #define PCI_READ(base,index,addr) \ {*(ULONG *)addr = PSWAP(*PCI_ADDR(base,index)); EIEIO_SYNC;} #define PCI_WRITE(base,index,data) \ {*PCI_ADDR(base,index) = PSWAP(data); EIEIO_SYNC; } #define CHAPARRAL_DATA_REG ((CHAPARRAL_REG << 16) | 0xCFC) #define CHAPARRAL_ADDR_REG ((CHAPARRAL_REG << 16) | 0xCF8) #define READ_CHAPARRAL_REG_UCHAR(reg, x) \ *(ULONG*)(CHAPARRAL_ADDR_REG)=((CHAPARRAL_REG << 16) | reg); \ ISYNC; \ (UCHAR)x=CHAPARRAL_DATA_REG+REG_OFF(reg)) #define READ_CHAPARRAL_REG_ULONG(reg, x) \ *(ULONG*)(CHAPARRAL_ADDR_REG)=REG_BASE(((CHAPARRAL_REG << 16) | reg)); \ ISYNC; \ (ULONG)x=CHAPARRAL_DATA_REG #if defined(INCLUDE_NETWORK) && defined(INCLUDE_END) /* network */ #if defined(INCLUDE_DEC_END) STATUS sysDec21x40PciInit (void); #endif /* INCLUDE_DEC_END */ #endif /* INCLUDE_NETWORK && INCLUDE_END */ IMPORT void sysIbcIntLevelSet (int intNum); IMPORT void sysEpicReset (void); IMPORT UINT sysTimeBaseUGet (); IMPORT UINT sysTimeBaseLGet (); IMPORT void sysTbInit (); IMPORT UINT sysHid1Get (); IMPORT UINT sysThrm1Get (); IMPORT void sysThrm1Set (); IMPORT UINT sysThrm2Get (); IMPORT void sysThrm2Set (); IMPORT UINT sysThrm3Get (); IMPORT void sysThrm3Set (); #if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L2) IMPORT UINT sysL2crGet(); #endif /* INCLUDE_CACHE_SUPPORT && INCLUDE_CACHE_L2 */ IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest); IMPORT int sysProbeExc(); /* globals */ /* * sysBatDesc[] is used to initialize the block address translation (BAT) * registers within the PowerPC 603/604 MMU. BAT hits take precedence * over Page Table Entry (PTE) hits and are faster. Overlap of memory * coverage by BATs and PTEs is permitted in cases where either the IBATs * or the DBATs do not provide the necessary mapping (PTEs apply to both * instruction AND data space, without distinction). * * The primary means of memory control for VxWorks is the MMU PTE support * provided by vmLib and cacheLib. Use of BAT registers will conflict * with vmLib support. User's may use BAT registers for i/o mapping and * other purposes but are cautioned that conflicts with cacheing and mapping * through vmLib may arise. Be aware that memory spaces mapped through a BAT * are not mapped by a PTE and any vmLib() or cacheLib() operations on such * areas will not be effective, nor will they report any error conditions. * * Note: BAT registers CANNOT be disabled - they are always active. * For example, setting them all to zero will yield four identical data * and instruction memory spaces starting at local address zero, each 128KB * in size, and each set as write-back and cache-enabled. Hence, the BAT regs * MUST be configured carefully. * * With this in mind, it is recommended that the BAT registers be used * to map LARGE memory areas external to the processor if possible. * If not possible, map sections of high RAM and/or PROM space where * fine grained control of memory access is not needed. This has the * beneficial effects of reducing PTE table size (8 bytes per 4k page) * and increasing the speed of access to the largest possible memory space. * Use the PTE table only for memory which needs fine grained (4KB pages) * control or which is too small to be mapped by the BAT regs. * * In the default CHRP address map all IBATs point to to flash ROM space and * four DBATs point to the 1GB VME A32 master window. * In the PReP address map the DBATs point to flash ROM space too. * */ #if (PCI_CFG_TYPE == PCI_CFG_AUTO) UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] = { /* I BAT 0 */ (((FLASH_BASE_ADRS | 0x00000) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512K | _MMU_UBAT_VS | _MMU_UBAT_VP), (((FLASH_BASE_ADRS | 0x00000) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* I BAT 1 */ (((FLASH_BASE_ADRS | 0x80000) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512K | _MMU_UBAT_VS | _MMU_UBAT_VP), (((FLASH_BASE_ADRS | 0x80000) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* I BAT 2 */ (((EXT_FLASH_BASE_ADRS | 0x00000000) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M | _MMU_UBAT_VS | _MMU_UBAT_VP), (((EXT_FLASH_BASE_ADRS | 0x00000000) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* I BAT 3 */ (((EXT_FLASH_BASE_ADRS | 0x02000000) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M | _MMU_UBAT_VS | _MMU_UBAT_VP), (((EXT_FLASH_BASE_ADRS | 0x02000000) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), #if defined (ADRS_MAP_PREP) /* D BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 1 */ ((EXT_FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_64M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((EXT_FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 2 */ 0, 0, /* D BAT 3 */ 0, 0, #else /* defined (ADRS_MAP_PREP) */ /* MODIFY A32 VME WINDOW HERE */ /* D BAT 0 */ ((((unsigned int)VME_A32_MSTR_LOCAL + 0*MEM_256MB) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((((unsigned int)VME_A32_MSTR_LOCAL + 0*MEM_256MB) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 1 */ ((((unsigned int)VME_A32_MSTR_LOCAL + 1*MEM_256MB) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((((unsigned int)VME_A32_MSTR_LOCAL + 1*MEM_256MB) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 2 */ ((((unsigned int)VME_A32_MSTR_LOCAL + 2*MEM_256MB) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((((unsigned int)VME_A32_MSTR_LOCAL + 2*MEM_256MB) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 3 */ ((((unsigned int)VME_A32_MSTR_LOCAL + 3*MEM_256MB) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((((unsigned int)VME_A32_MSTR_LOCAL + 3*MEM_256MB) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), #endif /* defined (ADRS_MAP_PREP) */ }; #else UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] = { /* I BAT 0 */ (((FLASH_BASE_ADRS | 0x00000) & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512K | _MMU_UBAT_VS | _MMU_UBAT_VP), (((FLASH_BASE_ADRS | 0x00000) & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_
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