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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b53603d2fbb000724ae18/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">同步<span class="_ _0"> </span><span class="ff2 sc1">fo<span class="_ _0"> </span></span>设计<span class="fs1"></span></div><div class="t m0 x1 h4 y3 ff3 fs1 fc0 sc1 ls0 ws0">1<span class="ff1">．功能定义：</span></div><div class="t m0 x1 h4 y4 ff3 fs1 fc0 sc1 ls0 ws0"><span class="_ _1"> </span><span class="ff1">用<span class="_ _0"> </span></span>16*8<span class="_ _2"></span> <span class="_ _2"></span>RAM<span class="_"> </span><span class="ff1">实<span class="_ _3"></span>现<span class="_ _3"></span>一<span class="_ _2"></span>个<span class="_ _3"></span>同<span class="_ _3"></span>步<span class="_ _2"></span>先<span class="_ _3"></span>进<span class="_ _4"></span>先<span class="_ _4"></span>出<span class="_ _4"></span>（<span class="_ _5"> </span></span>FIFO<span class="_ _4"></span><span class="ff1">）<span class="_ _4"></span>队<span class="_ _4"></span>列<span class="_ _4"></span>设<span class="_ _3"></span>计<span class="_ _4"></span>。<span class="_ _4"></span>由<span class="_ _4"></span>写<span class="_ _4"></span>使<span class="_ _4"></span>能<span class="_ _3"></span>端<span class="_ _4"></span>控<span class="_ _4"></span>制<span class="_ _4"></span>该<span class="_ _4"></span>数<span class="_ _3"></span>据<span class="_ _4"></span>流<span class="_ _4"></span>的<span class="_ _4"></span>写<span class="_ _4"></span>入</span></div><div class="t m0 x1 h4 y5 ff3 fs1 fc0 sc1 ls0 ws0">FIFO<span class="_ _2"></span><span class="ff1">，并由<span class="_ _2"></span>读使<span class="_ _2"></span>能控制<span class="_ _6"> </span></span>FIFO<span class="_ _7"> </span><span class="ff1">中数<span class="_ _2"></span>据的<span class="_ _2"></span>读出<span class="_ _8"></span>。写<span class="_ _8"></span>入<span class="_ _8"></span>和<span class="_ _8"></span>读出<span class="_ _8"></span>的<span class="_ _8"></span>操<span class="_ _8"></span>作<span class="_ _8"></span>由<span class="_ _8"></span>时钟<span class="_ _8"></span>的<span class="_ _8"></span>上<span class="_ _8"></span>升沿<span class="_ _8"></span>触<span class="_ _8"></span>发<span class="_ _8"></span>。<span class="_ _8"></span>当<span class="_ _6"> </span></span>FIFO<span class="_ _7"> </span><span class="ff1">的<span class="_ _8"></span>数</span></div><div class="t m0 x1 h4 y6 ff1 fs1 fc0 sc1 ls0 ws0">据满和空的时候分别设置相应的高电平加以指示。</div><div class="t m0 x1 h4 y7 ff3 fs1 fc0 sc1 ls0 ws0">2<span class="ff1">．顶层信号定义：</span></div><div class="t m0 x2 h5 y8 ff1 fs2 fc1 sc1 ls0 ws0">信号名称</div><div class="t m0 x3 h6 y9 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x4 h5 y8 ff1 fs2 fc1 sc1 ls0 ws0">功能描述<span class="_ _9"> </span>源<span class="ff4"></span>目标<span class="_ _a"> </span>备注</div><div class="t m0 x2 h6 ya ff4 fs2 fc1 sc1 ls0 ws0"><span class="_ _b"> </span></div><div class="t m0 x4 h5 yb ff1 fs2 fc1 sc1 ls0 ws0">全局复位（低有效）<span class="_ _c"> </span>管脚</div><div class="t m0 x5 h6 ya ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h6 yc ff4 fs2 fc1 sc1 ls0 ws0"><span class="_ _d"> </span></div><div class="t m0 x4 h5 yd ff1 fs2 fc1 sc1 ls0 ws0">全局时钟<span class="_ _9"> </span>管脚<span class="_ _e"> </span>频<span class="_ _f"> </span>率<span class="_ _10"> </span><span class="ff4"><span class="_ _f"> </span></span>占<span class="_ _f"> </span>空<span class="_ _f"> </span>比<span class="_ _f"> </span>：</div><div class="t m0 x5 h6 ye ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h6 yf ff4 fs2 fc1 sc1 ls0 ws0"><span class="_ _11"> </span></div><div class="t m0 x4 h5 y10 ff1 fs2 fc1 sc1 ls0 ws0">低有效写使能<span class="_ _12"> </span>管脚</div><div class="t m0 x5 h6 yf ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h6 y11 ff4 fs2 fc1 sc1 ls0 ws0"><span class="_ _13"> </span></div><div class="t m0 x4 h5 y12 ff1 fs2 fc1 sc1 ls0 ws0">低有效读使能<span class="_ _12"> </span>管脚</div><div class="t m0 x5 h6 y11 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h5 y13 ff4 fs2 fc1 sc1 ls0 ws0"><span class="ff1">：</span></div><div class="t m0 x2 h6 y14 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x3 h6 y15 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x4 h5 y13 ff1 fs2 fc1 sc1 ls0 ws0">数据输入端<span class="_ _14"> </span>管脚</div><div class="t m0 x5 h6 y15 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h5 y16 ff4 fs2 fc1 sc1 ls0 ws0"> <span class="ff1">：</span></div><div class="t m0 x3 h6 y17 ff4 fs2 fc1 sc1 ls0 ws0"> </div><div class="t m0 x4 h5 y16 ff1 fs2 fc1 sc1 ls0 ws0">数据输出端<span class="_ _14"> </span>管脚</div><div class="t m0 x5 h6 y17 ff4 fs2 fc1 sc1 ls0 ws0"></div><div class="t m0 x2 h6 y18 ff4 fs2 fc1 sc1 ls0 ws0">!"#$<span class="_ _15"> </span> </div><div class="t m0 x4 h5 y19 ff1 fs2 fc1 sc1 ls0 ws0">空指示信号<span class="_ _14"> </span>管脚<span class="_ _e"> </span>为高时表示<span class="_ _7"> </span><span class="ff4">%&<span class="_ _7"> </span></span>空</div><div class="t m0 x2 h6 y1a ff4 fs2 fc1 sc1 ls0 ws0">' <span class="_ _16"> </span> </div><div class="t m0 x4 h5 y1b ff1 fs2 fc1 sc1 ls0 ws0">满指示信号<span class="_ _14"> </span>管脚<span class="_ _e"> </span>为高时表示<span class="_ _7"> </span><span class="ff4">%&<span class="_ _7"> </span></span>满</div><div class="t m0 x1 h4 y1c ff3 fs1 fc0 sc1 ls0 ws0">3<span class="ff1">．顶层模块划分及功能实现</span></div><div class="t m0 x1 h4 y1d ff1 fs1 fc0 sc1 ls0 ws0">该同步<span class="_ _17"> </span><span class="ff3">fifo<span class="_ _17"> </span></span>可划分为如下四个模块，如图<span class="_ _17"> </span><span class="ff3">1<span class="_ _17"> </span></span>所示：</div><div class="t m0 x6 h4 y1e ff4 fs1 fc0 sc1 ls0 ws0">(<span class="_ _17"> </span><span class="ff1">存储器模块（<span class="ff3">RAM</span>）——用于存放及输出数据；</span></div><div class="t m0 x6 h4 y1f ff4 fs1 fc0 sc1 ls0 ws0">)<span class="_ _17"> </span><span class="ff1">读地址模块<span class="ff3">(rd_addr)——</span>用于读地址的产生；</span></div><div class="t m0 x6 h4 y20 ff4 fs1 fc0 sc1 ls0 ws0">*<span class="_ _17"> </span><span class="ff1">写地址模块（<span class="ff3">wr_addr</span>）——用于写地址的产生</span></div><div class="t m0 x6 h4 y21 ff4 fs1 fc0 sc1 ls0 ws0">+<span class="_ _17"> </span><span class="ff1">标志模块（<span class="ff3">flag_gen</span>）<span class="ff3">----</span>用于产生<span class="_ _17"> </span><span class="ff3">FIFO<span class="_ _17"> </span></span>当前空满状态。</span></div></div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
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synchronous-FIFO.rar
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同步fifo的使用verilog案例讲解
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- 同步FIFO设计.doc324KB
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